Page 1 MVME5100 Single Board Computer Programmer’s Reference Guide V5100A/PG2 September 2001 Edition...
Page 2 © Copyright 2001 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola and the Motorola logo are registered trademarks and AltiVec is a trademark of Motorola, Inc. PowerPC and the PowerPC logo are registered trademarks; and PowerPC 750 is a trademark of International Business Machines Corporation and are used by Motorola, Inc.
Page 3 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
Page 4 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
Page 5 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Page 6 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013...
Page 7: Table Of Contents
Contents About This Manual Summary of Changes ....................xxiv Overview of Contents ....................xxiv Comments and Suggestions ..................xxv Conventions Used in This Manual................xxvi Terminology......................xxvi CHAPTER 1 Product Data and Memory Maps Introduction........................1-1 Memory maps ......................1-4 Processor Memory Map..................1-4 Default Processor Memory Map..............1-4 Processor Memory Map................1-5 PCI Memory Map ..................1-7 VME Memory Map ..................1-7...
Page 8 The Universe ASIC ..................1-17 PCI Configuration Space.................. 1-19 Hawk External Register Bus Address Assignments......... 1-21 MVME5100 Hawk External Register Bus Summary ....... 1-21 Dual TL16C550 UARTs................... 1-23 Status Register ....................1-24 MODFAIL Bit Register ..................1-25 MODRST Bit Register ..................1-26 TBEN Bit Register ...................
Page 9 When PPC Devices are Little Endian............2-39 PHB Registers....................2-40 Error Handling ....................2-41 Watchdog Timers ....................2-42 PCI/PPC Contention Handling .................2-45 Transaction Ordering ..................2-48 PHB Hardware Configuration ................2-49 Multi-Processor Interrupt Controller (MPIC) ............2-51 MPIC Features: ....................2-51 Architecture ......................2-51 External Interrupt Interface................2-52 CSR’s Readability.....................2-53 Interrupt Source Priority ...................2-53 Processor’s Current Task Priority ..............2-54 Nesting of Interrupt Events................2-54...
Page 10 PPC Registers ....................2-68 Vendor ID/Device ID Registers ..............2-70 Revision ID Register ................. 2-70 General Control-Status/Feature Registers..........2-71 PPC Arbiter/PCI Arbiter Control Registers ..........2-73 Hardware Control-Status/Prescaler Adjust Register ......... 2-77 PPC Error Test/Error Enable Register ............2-79 PPC Error Status Register ................. 2-82 PPC Error Address Register..............
Page 11 External Source Vector/Priority Registers ..........2-122 External Source Destination Registers ............2-124 Hawk Internal Error Interrupt Vector/Priority Register ......2-125 Hawk Internal Error Interrupt Destination Register ........2-126 Interprocessor Interrupt Dispatch Registers ..........2-126 Current Task Priority Registers ...............2-127 Interrupt Acknowledge Registers ............2-127 End-of-Interrupt Registers...............2-128 CHAPTER 3 System Memory Controller (SMC) Introduction........................3-1...
Page 12 I2C Current Address Read ................ 3-27 I2C Page Write ..................3-29 I2C Sequential Read.................. 3-31 Refresh/Scrub ....................3-34 CSR Accesses....................3-34 External Register Set ..................3-34 Chip Configuration................... 3-35 Programming Model....................3-35 CSR Architecture ..................... 3-35 Register Summary .................... 3-36 Detailed Register Bit Descriptions ..............
Page 13 Endian Issues ......................4-7 Processor/Memory Domain ................4-9 MPIC’s Involvement...................4-9 PCI Domain ......................4-9 APPENDIX A Related Documentation Motorola Computer Group Documents ..............A-1 Manufacturers’ Documents..................A-2 Related Specifications....................A-4 APPENDIX B MVME5100 VPD Reference Information Vital Product Data (VPD) Introduction ..............B-1 How to Read the VPD Information ..............B-1 How to Modify the VPD Information..............
Page 14 How to Fix Wrong VPD Problems..............B-3 VPD Definitions - Packet Types................ B-4 VPD Definitions - Product Configuration Options Data........B-7 VPD Definitions - FLASH Memory Configuration Data ......... B-9 VPD Definitions - L2 Cache Configuration Data ........... B-10 VPD Definitions - VPD Revision Data ............B-12 Configuration Checksum Calculation Code..........
Page 15 List of Figures Figure 1-1. MVME5100 Block Diagram ..............1-3 Figure 1-2. VMEbus Master Mapping..............1-18 Figure 2-1. Hawk PCI Host Bridge Block Diagram ..........2-3 Figure 2-2. PPC to PCI Address Decoding..............2-6 Figure 2-3. PPC to PCI Address Translation .............2-7 Figure 2-4. PCI to PPC Address Decoding..............2-20 Figure 2-5.
Page 17 Table 1-8. On-Board PCI Device Identification ............1-20 Table 1-9. Hawk External Register Bus Summary ..........1-21 Table 1-10. 16550 Access Registers ................1-23 Table 1-11. MVME5100 Status Register ..............1-24 Table 1-12. MODFAIL Bit Register ................1-25 Table 1-13. MODRST Bit Register................1-26 Table 1-14. TBEN Bit Register ................1-27 Table 1-15.
Page 18 Table 3-22. Single Bit Errors Ordered by Syndrome Code ........3-87 Table 4-1. MPIC Interrupt Assignments..............4-1 Table 4-2. PBC ISA Interrupt Assignments .............. 4-3 Table 4-3. Error Notification and Handling............... 4-6 Table A-1. Motorola Computer Group Documents ..........A-1 Table A-2. Manufacturers’ Documents ..............A-2 xviii...
Page 19 Table A-3. Related Specifications ................A-4 Table B-1. VPD Packet Types................... B-4 Table B-2. MCG Product Configuration Options Data..........B-7 Table B-3. FLASH Memory Configuration Data ............. B-9 Table B-4. L2 Cache Configuration Data ............... B-10 Table B-5. VPD Revision Data ................B-12...
Page 21: About This Manual
This guide provides programming information and other data applicable to the MVME5100. As an added convienience, it also provides details of the chip set (Hawk) programming functions. It is important to note that much of the board’s programming functionality is associated with the Hawk...
Page 22 As of the printing date of this manual, the MVME5100 is available in the configurations shown below. Model Description MPC750 configurations with 450 MHz MPC750, 17MB Flash and 1MB L2 Cache MVME5100-0131 64MB ECC SDRAM, SCANBE handles MVME5100-0161 512MB ECC SDRAM, SCANBE handles...
Page 23 I/O Modules MVME712M Compatible I/O IPMC712-001 Multifunction rear I/O PMC module; Ultra Wide SCSI, one parallel port, three sync and one sync/async serial ports. MVME712M Transition module connectors: One DB-25 sync/async serial port, three DB-25 async serial port, one AUI connector, one D-36 parallel port, and one 50-pin 8-bit SCSI;...
Page 24: Summary Of Changes
"About this Manual" was also added. Overview of Contents The following paragraphs briefly describe the contents of each chapter. Chapter 1, Product Data and Memory Maps, provides a description of the MVME5100, tables of specific memory maps and other control registers. xxiv...
Page 25: Comments And Suggestions
VPD Data Definitions. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:...
Page 26: Conventions Used In This Manual
In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.
Page 27 Specifies a binary number & Specifies a decimal number An asterisk (*) following a signal name for signals that are level significant denotes that the signal is true or valid when the signal is low. An asterisk (*) following a signal name for signals that are edge significant denotes that the actions initiated by that signal occur on high to low transition.
Page 28 xxviii...
Page 29: Introduction
100 MHz. Note Unless otherwise specified, the designation “MVME5100” refers to all models of the MVME5100-series Single Board Computers. The following table lists the key features of the MVME5100. Table 1-1. MVME Key Features Feature Specification Microprocessors and • MPC7400 @400 MHz Internal Clock Frequency Bus Clock Frequency •...
Page 30 Product Data and Memory Maps Table 1-1. MVME Key Features (Continued) Feature Specification Main Memory • PC100 ECC SDRAM with 100 MHz bus (SDRAM) • 32MB to 512MB on board, expandable to 1GB via RAM500 memory mezzanine NVRAM • 32KB (4KB available for users) Memory Controller •...
Page 31: Figure 1-1. Mvme5100 Block Diagram
PCI Host Bridge (PHB) RTC/NVRAM/WD M48T37V Hawk X-bus 33 MHz 32/64-bit PCI Local Bus TL16C550 UART VME Bridge Ethernet 1 Ethernet 2 Universe 2 10/100TX 10/100TX Buffers 761 or PMC VME P2 VME P1 Figure 1-1. MVME5100 Block Diagram http://www.motorola.com/computer/literature...
Page 32: Memory Maps
Following a reset, the memory map presented to the processor is identical to the CHRP memory map described in this document. The MVME5100 is fully capable of supporting both the PREP and the CHRP processor memory maps with ROM/FLASH size limited to 16MB and RAM size limited to 2GB.
Page 33: Processor Memory Map
PCI Memory Space is determined by the end of DRAM rounded up to the nearest 256MB-boundry as required by CHRP. For example, if memory was 1G on the baseboard and 192MB on a mezzanine, the beginning of PCI memory would be rounded up to address 0x50000000 (1G + 256M). http://www.motorola.com/computer/literature...
Page 34: Table 1-3. Suggested Chrp Memory Map
Product Data and Memory Maps Table 1-3. Suggested CHRP Memory Map Processor Address Size Definition Notes Start 0000 0000 top_dram dram_size System Memory (onboard DRAM) top_dram F3FF FFFF 4G-dram_size PCI Memory Space 1, 5 F400 0000 F7FF FFFF 64MB FLASH Bank A (optional) 1, 2 F800 0000 FBFF FFFF...
Page 35: Pci Memory Map
PCI Memory Map Following a reset, the Hawk ASIC disable’s all PCI slave map decoders. The MVME5100 is fully capable of supporting both PREP and CHRP PCI Memory Maps with RAM size limited to 2GB. The default values for the PCI Slave Image registers, are listed in Chapter 3, PPCBug, of the MVME5100 Single Board Computer Installation and Use manual.
Page 36: Pci Local Bus Memory Map
PREP-compatible memory maps, can be found in the Hawk portion of this manual (Chapters 2 and 3). System Bus The following sections describe the processor system bus for the MVME5100. Only the PPC60x bus interface is supported. Computer Group Literature Center Web Site...
Page 37: Processors
System Bus Processors The MVME5100 has the BGA foot print that supports the MPC750 and MPC7400 processors. The maximum external processor bus speed is 100 MHz. Parity checking is supported for the system address and data busses. Processor Type Identification The processor version can be determined by reading the Processor Version Register (PVR).
Page 38: L2 Cache Sram Size
FLASH Memory The MVME5100 contains two banks of FLASH memory. Bank B consists of two 32-pin devices that can be populated with 1MB of FLASH memory. Only 8-bit writes are supported for this bank. Bank A has 4 16-bit Smart Voltage FLASH SMT devices.
Page 39: Ecc Memory
Hawk ASIC. P2 I/O Modes The MVME5100 has two P2 I/O modes (SBC and PMC) that are user configurable with 4 jumpers on the planar (refer to the jumper settings in the MVME5100 Single Board Computer Installation and Use manual).
Page 40: Serial Presence Detect (Spd) Definitions
MVME2400 models. The SBC mode is accomplished by configuring planar jumpers and attaching an IPMC761 PMC card in PMC slot 1 of the MVME5100. Refer to the IPMC712/761 I/O Module Installation and Use manual for additional installation and programming information. PMC mode is accomplished by configuring planar jumpers.
Page 41: Hawk I2C Interface And Configuration Information
There can be seven slave devices connected to the I C bus on the MVME5100. The VPD address is $A0. The UPD address is $A2. The on-board MSD address (Memory Bank A and B) is $A8. The optional Memory Mezzanine 1 MSD addresses is $AA (Memory Bank C) and $AC (Memory Bank E) for mezzanine 2.
Page 42: Vital Product Data (Vpd) And Serial Presence Detect (Spd) Data
For information on the VPD and SPD data formats and defintions refer to Appendix B, MVME5100 VPD Reference Information. The registers related to this information is accessed through the I interface of the Hawk ASIC.
Page 43: Pci Local Bus
Table 1-6. PCI Arbitration Assignments PCI Bus Request PCI Master(s) Request 0 (PARBI0) Universe ASIC (VMEbus) PARBI0 Request 1 (PARBI1) PMC Slot 1 (SCSI device on IPMC761 in PMC Slot 1)* Request 2 (PARBI2) PIB device on IPMC761 in PMC Slot 1* http://www.motorola.com/computer/literature 1-15...
Page 44: The Ethernet Controller
*Refer to the IPMC712/761 I/O Module Installation and Use manual. The Ethernet Controller The MVME5100 provides dual Ethernet interfaces (Port 1 and Port 2) via two pairs of Intel GD82559ER Fast Ethernet PCI controller chips. Port 1’s 10BaseT/100BaseTx interface is routed through the front panel. Port 2’s Ethernet interface is routed to either the front panel or the P2 connector, as configured by jumpers.
Page 45: Pmc/Pci Expansion Slots
Up to two PMC slots and one PCIX slot may be present. The presence of the PMCs and/or PCIX can be positively determined by reading the Base Module Feature Register. The INTA#, INTB#, INTC#, and INTD# from the three PMC/PCIX slots are routed by the MVME5100 as follows: PMC Slot 1 PMC Slot 2...
Page 46: Figure 1-2. Vmebus Master Mapping
Product Data and Memory Maps VMEBUS PROCESSOR PCI MEMORY ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 NOTE 1 PCI MEMORY SPACE VME A24 VME A16 NOTE 3 VME A24 VME A16 NOTE 1 VME A24 PCI/ISA MEMORY SPACE VME A16 VME A24 I/O SPACE VME A16 RESOURCES...
Page 47: Pci Configuration Space
CONADD and CONDAT Registers. The location and operation of these registers is fully described in the section titled Generating PCI Configuration Cycles in Chapter 2. The IDSEL assignments for MVME5100 are shown on the following table: Table 1-7. IDSEL Mapping for PCI Devices Device Number Address...
Page 48: Table 1-8. On-Board Pci Device Identification
Product Data and Memory Maps The following table shows the current Vendor ID, the Device ID, and the Revision ID for each of the on-board PCI devices on the MVME5100: Table 1-8. On-Board PCI Device Identification Device Device Vendor ID...
Page 49: Hawk External Register Bus Address Assignments
Address Assignments on MVME5100. The address range for the External Register Set on MVME5100 is fixed at $FEF88000-$FEF8FFFF. MVME5100 Hawk External Register Bus Summary The Hawk External Register Summary of the MVME5100 is shown in the table below: Table 1-9. Hawk External Register Bus Summary...
Page 50 Product Data and Memory Maps Table 1-9. Hawk External Register Bus Summary (Continued) Bits: REQUIRED (r) Address OPTIONAL (o) Register Name by PowerPlus II 0 1 2 3 4 5 6 7 $FEF880C8 NVRAM/RTC ADDR THIS GROUP $FEF880D0 NVRAM/RTC ADDR OPTIONAL $FEF880D8 NVRAM/RTC DATA...
Page 51: Dual Tl16C550 Uarts
PCI Local Bus Dual TL16C550 UARTs The MVME5100 implementation of the Dual TL16C550 UARTs are fully compliant with the PowerPlus II Programming Model for UART Registers. The following tables reflect this model. The MVME5100 uses UART-1 and UART-2 for asynchronous serial debug ports (four are allowed by the PowerPlus II Programming Model).
Page 52: Status Register
Product Data and Memory Maps Status Register The MVME5100 implementation of this Register is fully compliant with the PowerPlus II programming model, with exceptions to bits RD5, RD6 and RD7, as identified in the following table: An 8-bit status register, accessible through the External Register Set port, defines the status of the Module.
Page 53: Modfail Bit Register
PCI Local Bus MODFAIL Bit Register The MVME5100 implementation of this register is fully compliant with the PowerPlusII programming specification with exceptions to bit RD5, as indicated in the following table: The MODFAIL Bit Register provides the means to illuminate the module’s Board Fail LED.
Page 54: Modrst Bit Register
Product Data and Memory Maps MODRST Bit Register The MODRST Bit register provides the means to reset the board. Table 1-13. MODRST Bit Register Module Reset Bit Register - FEF880A0h FIELD OPER RESET MODRST Setting this bit resets the module. This bit will automatically clear following the reset.
Page 55: Tben Bit Register
PCI Local Bus TBEN Bit Register The MVME5100 implementation of this register is fully compliant with the PowerPlus II Programming Specification, with exceptions to Bit RD6, as indicated in the following table: The TBEN Bit register provides the means to control the Processor Timebase Enable input.
Page 56: Nvram/Rtc & Watchdog Timer
Product Data and Memory Maps NVRAM/RTC & Watchdog Timer The MVME5100’s NVRAM/RTC and Watchdog Timer functions are supplied by an M48T37V device and is fully compliant with the PowerPlusII internal programming configuration. The M48T37V provides 32K of non-volatile SRAM, a time-of-day clock, and a watchdog timer.
Page 57: Software Readable Header/Switch Register (S1)
PCI Local Bus Software Readable Header/Switch Register (S1) The MVME5100’s use of this register is fully compliant with the PowerPlus II internal programming configuration. A 1x8 header/switch (S1) is provided as the Software Readable Header/Switch (SRH). A logic 0 means the header/switch is in the "on" position for that particular bit and a logic 1 means the header/switch is in the "off"...
Page 58: Geographical Address Register (Vme Board)
Product Data and Memory Maps Geographical Address Register (VME board) The following register provides geographical address status. The Geographical Address Register is an 8-bit read-only register.This register reflects the states of the geographical address pins on the 5-row, 160-pin P1 connector. Geographical Address Register - Offset 80E8h FIELD GAP#...
Page 59: Extended Features Register 1
MMEZ1_P_L Memory Mezzanine 1 present. When set there is no memory mezzanine 1 present. When cleared, there is a memory mezzanine 1 present. MMEZ2_P_L Memory Mezzanine 2 present. When set, there is no memory mezzanine 1 present. When cleared, there is a memory mezzanine 2 present. http://www.motorola.com/computer/literature 1-31...
Page 60: Board Last Reset Register
CPCIRST CompactPCI Reset. If set, a CompactPCI RST# reset has occurred. Not applicable for the MVME5100. CMDRST CompactPCI Command Reset. If set, a software reset command has been issued to the 21554 bridge from the CompactPCI bus.
Page 61: Extended Features Register 2
Table 1-17. Extended Features Register 2 Extended Features Register 2 - Offset 80F0h FIELD OPER RESET REQUIRED OPTIONAL PCIXP_L PCI Expansion Slot Present. If set, there is no PCIX device installed. If cleared, the PCIX slot contains a PCI Mezzanine Card. http://www.motorola.com/computer/literature 1-33...
Page 62 Product Data and Memory Maps 1-34 Computer Group Literature Center Web Site...
Page 63: Introduction
2Hawk PCI Host Bridge & Multi- Processor Interrupt Controller Introduction Overview This chapter describes the architecture and usage of the PowerPC to PCI Host Bridge (PHB) and the Multi-Processor Interrupt Controller (MPIC) portion of the Hawk ASIC. The Hawk is intended to provide PowerPC 60x (PPC60x bus) compliant devices access to devices residing on the PCI Local Bus.
Page 64 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller – Read-ahead buffer for reads from the PPC bus. – Four independent software programmable slave map decoders. Interrupt Controller – MPIC compliant. – MPIC programming model. – Support for 16 external interrupt sources and two processors. –...
Page 65: Block Diagram
Block Diagram Block Diagram Figure 2-1. Hawk PCI Host Bridge Block Diagram http://www.motorola.com/computer/literature...
Page 66: Functional Description
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Functional Description Architectural Overview A functional block diagram of the Hawk’s PCI Host Bridge (PHB) is shown in Figure 2-1. The PHB control logic is subdivided into the following functions: PCI Slave, PCI Master, PPC Slave and PPC Master. The PHB data path logic is subdivided into the following functions: PCI FIFO, PPC FIFO, PCI Input, PPC Input, PCI Output, and PPC Output.
Page 67: Ppc Bus Interface
PCI Parity block. PPC Bus Interface The PPC Bus Interface connects directly to one MPC750 or MPC7400 microprocessor and one peripheral PPC60x master device. It uses a subset of the capabilities of the PPC bus protocol. http://www.motorola.com/computer/literature...
Page 68: Ppc Address Mapping
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Address Mapping The PHB will map either PCI memory space or PCI I/O space into PPC address space using four programmable map decoders. These decoders provide windows of access to the PCI bus from the PPC bus. The most significant 16 bits of the PPC address are compared with the address range of each map decoder, and if the address falls within the specified range, the access is passed on to the PCI.
Page 69: Ppc Slave
PPC Slave will hold off asserting AACK_ and TA_ until after the transaction has completed on the PCI bus. This has the effect of removing all levels of pipelining during compelled PHB accesses. The interdependency between the assertion of http://www.motorola.com/computer/literature...
Page 70: Table 2-1. Ppc Slave Response Command Types
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller AACK_ and TA_ allows the PPC Slave to assert a retry to the processor in the event that the transaction is unable to complete on the PCI side. It should be noted that any transaction that crosses a PCI word boundary could be disrupted after only having a portion of the data transferred.
Page 71: Ppc Fifo
PPC Slave and the PCI Master. If write posting has been enabled, then the maximum number of transactions that may be posted is limited by the abilities of either the data FIFO or the command FIFO. http://www.motorola.com/computer/literature...
Page 72: Ppc Master
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller For example, two burst transactions make the data FIFO the limiting factor for write posting. Four single beat transactions make the command FIFO the limiting factor. If either limit is exceeded, then any pending PPC transactions is delayed (AACK_ and TA_ are not asserted) until the PCI Master has completed a portion of the previously posted transactions and created some room within the command and/or data FIFOs.
Page 73: Table 2-2. Ppc Master Transaction Profiles And Starting Offsets
PCI Slave is continuously stalling during write posted transactions, then further tuning might be needed. This can be accomplished by changing the WXFT (Write Any Fifo Threshold) field within the PSATTx registers to recharacterize PHB write posting mechanism. The FIFO http://www.motorola.com/computer/literature 2-11...
Page 74: Table 2-3. Ppc Master Write Posting Options
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller threshold should be lowered to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus. Table 2-3 summarizes the PHB available write posting options. Table 2-3. PPC Master Write Posting Options WXFT WPEN PPC60x Start...
Page 75 PCI Slave map decoders. As an example, assume PHB has been programmed to respond to PCI address range $10000000 through $1001FFFF with an offset of $2000. The PPC Master performs its last read on the PPC60x bus at cache line address $3001FFFC or word address $3001FFF8. http://www.motorola.com/computer/literature 2-13...
Page 76: Table 2-5. Ppc Master Transfer Types
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PPC60x bus transfer types generated by the PPC Master depend on the PCI command code and the INV/GBL bits in the PSATTx registers. The GBL bit determines whether or not the GBL_ signal is asserted for all portions of a transaction and is fully independent of the PCI command code and INV bit.
Page 77: Ppc Arbiter
Output CPU1 Grant_ Input CPU1 Grant_ XARB2 BiDir Tristate Output EXTL Grant_ Input EXTL Grant_ XARB3 BiDir Tristate Input CPU0 Request_ Output HAWK Request_ XARB4 Input Input CPU1 Request_ Input HAWK Grant_ XARB5 Input Input EXTL Request_ Input http://www.motorola.com/computer/literature 2-15...
Page 78 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller While RST_ is asserted, XARB0 through XARB4 is held in tri-state. If the internal arbiter mode is selected, then XARB0 through XARB3 is driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST_.
Page 79: Ppc Parity
Address parity errors can only be injected during cycles where PHB is sourcing a PPC address. The PHB does not have the ability to check for address parity errors. http://www.motorola.com/computer/literature 2-17...
Page 80: Ppc Bus Timer
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Bus Timer The PPC Timer allows the current bus master to recover from a potential lock-up condition caused when there is no response to a transfer request. The time-out length of the bus timer is determined by the XBT field within the GCSR.
Page 81: Pci Bus Interface
PCI Memory space. The mapping of PPC address space is handled by device specific registers located above the 64 byte header. These control registers support a mapping scheme that is functionally similar to the PCI- to-PPC mapping scheme described in the section titled PPC Address Mapping. http://www.motorola.com/computer/literature 2-19...
Page 82: Figure 2-4. Pci To Ppc Address Decoding
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Bus Address Space The PHB maps PPC address space into PCI Memory space using four programmable map decoders. The most significant 16 bits of the PCI address is compared with the address range of each map decoder, and if the address falls within the specified range, the access is passed on to the PPC bus.
Page 83: Figure 2-5. Pci To Ppc Address Translation
The decoders are prioritized as shown below. Decoder Priority PCI Slave 0 highest PCI Slave 1 PCI Slave 2 PCI Slave 3 lowest http://www.motorola.com/computer/literature 2-21...
Page 84: Pci Slave
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC Control Registers The MPIC control registers are located within either PCI Memory or PCI I/O space using traditional PCI defined base registers within the predefined 64-byte header. Refer to the section titled Multi-Processor Interrupt Controller (MPIC) for more information.
Page 85: Table 2-7. Pci Slave Response Command Types
PCI Slave returns an entire word of data regardless of the byte enables. During I/O read cycles, the PCI Slave performs integrity checking of the byte enables against the address being presented and assert SERR* in the event there is an error. http://www.motorola.com/computer/literature 2-23...
Page 86 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave only honors the Linear Incrementing addressing mode. The PCI Slave performs a disconnect with data if any other mode of addressing is attempted. Device Selection The PCI slave will always respond valid decoded cycles as a medium responder.
Page 87 PHB results in the PCI Slave issuing a retry. Parity The PCI Slave supports address parity error detection, data parity generation, and data parity error detection. Cache Support The PCI Slave does not participate in the PCI caching protocol. http://www.motorola.com/computer/literature 2-25...
Page 88: Pci Fifo
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI FIFO A 64-bit by 16 entry FIFO (4 cache lines total) is used to hold data between the PCI Slave and the PPC Master to ensure that optimum data throughput is maintained. The same FIFO is used for both read and write transactions. A 52-bit by 4 entry FIFO is used to hold command information being passed between the PCI Slave and the PPC Master.
Page 89: Table 2-8. Pci Master Command Codes
PPC Mapped PCI Space Read 0110 Memory Read Write 0111 Memory Write -- Unsupported -- 1000 Reserved -- Unsupported -- 1001 Reserved CONADD/CONDAT Read 1010 Configuration Read CONADD/CONDAT Write 1011 Configuration Write -- Unsupported -- 1100 Memory Read Multiple http://www.motorola.com/computer/literature 2-27...
Page 90 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-8. PCI Master Command Codes (Continued) Entity Addressed TBST* C/BE PCI Command Transfer Type -- Unsupported -- 1101 Dual Address Cycle PPC Mapped PCI Space Read 1110 Memory Read Line -- Unsupported -- 1111 Memory Write and Invalidate...
Page 91: Generating Pci Cycles
The PCI Master does not participate in the PCI caching protocol. Generating PCI Cycles There are four basic types of bus cycles that can be generated on the PCI bus: Memory and I/O Configuration Special Cycle Interrupt Acknowledge http://www.motorola.com/computer/literature 2-29...
Page 92 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Memory and I/O Cycles Each programmable slave may be configured to generate PCI I/O or memory accesses through the MEM and IOM fields in its XSATTx register as shown below. PCI Cycle Type Memory Contiguous I/O...
Page 93: Figure 2-6. Pci Spread I/O Address Translation
Performing a configuration access is a two step process. The first step is to place the address of the configuration cycle within the CONFIG_ADDRESS register. Note that this action does not generate any cycles on the PCI bus. http://www.motorola.com/computer/literature 2-31...
Page 94 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The second step is to either read or write configuration data into the CONFIG_DATA register. If the CONFIG_ADDRESS register is set up correctly, the PHB will pass this access on to the PCI bus as a configuration cycle.
Page 95 After the write to CONFIG_ADDRESS has been accomplished, the next write to the CONFIG_DATA register causes the PHB to generate a special cycle on the PCI bus. The write data is driven onto AD[31:0] during the special cycle’s data phase. http://www.motorola.com/computer/literature 2-33...
Page 96: Pci Arbiter
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Interrupt Acknowledge Cycles Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge cycle. Any single byte or combination of bytes may be read from, and the actual byte enable pattern used during the read will be passed on to the PCI bus.
Page 97: Table 2-10. Fixed Mode Priority Level Setting
Notes 1. “000” is the default setting in fixed mode. 2. The HEIR setting only covers a small subset of all possible combinations. It is the responsibility of the system designer to connect the request/grant pair in a manner most beneficial to their design goals. http://www.motorola.com/computer/literature 2-35...
Page 98: Table 2-11. Mixed Mode Priority Level Setting
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When the arbiter is programmed for round robin priority mode, the arbiter maintains fairness and provides equal opportunity to the requestors by rotating its grants. The contents in “HEIR” field are “don’t cares” when operated in this mode.
Page 99: Table 2-12. Arbitration Setting
Park on last requestor 0001 Park on PARB6 0010 Park on PARB5 0011 Park on PARB4 0100 Park on PARB3 0101 Park on PARB2 0110 Park on PARB1 0111 Park on PARB0 1000 Park on HAWK 1111 Parking disabled http://www.motorola.com/computer/literature 2-37...
Page 100: Endian Conversion
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Notes 1. “1000” is the default setting. 2. Parking disabled is a test mode only and should not be used, since no one will drive the PCI bus when in an idle state.
Page 101: When Ppc Devices Are Little Endian
Figure 2-7. Big-to-Little-Endian Data Swap When PPC Devices are Little Endian When all PPC devices are operating in little-endian mode, the originating address is modified to remove the exclusive-ORing applied by PPC60x processors. Note that no data swapping is performed. http://www.motorola.com/computer/literature 2-39...
Page 102: Phb Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Address modification happens to the originating address regardless of whether the transaction originates from the PCI bus or the PPC bus. The three low order address bits are exclusive-ORed with a three-bit value that depends on the length of the operand, as shown in Table 2-13.
Page 103: Error Handling
Each bit in the ESTAT may be cleared by writing a 1 to it; writing a 0 to it has no effect. New error bits may be set only when all previous error bits have been cleared. http://www.motorola.com/computer/literature 2-41...
Page 104: Watchdog Timers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When any bit in the ESTAT is set, the PHB will attempt to latch as much information as possible about the error in the PPC Error Address (EADDR) and Attribute Registers (EATTR). Information is saved as follows: Error Error Address and...
Page 105 WDTxCNTL register. The KEY field byte lane must be selected and must be written with PATTERN_2 for the write to take affect. The effects on the WDTxCNTL register depend on the byte lanes that are written to during step 2 and are shown in Table 2-14. http://www.motorola.com/computer/literature 2-43...
Page 106: Table 2-14. Wdtxcntl Programming
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-14. WDTxCNTL Programming Byte Lane Selection Results ENAB RELOAD WDTxCNTL Register /RES 8:15 16:23 24:31 Prescaler/ Counter RES/ENAB RELOAD Enable No Change No Change No Change No Change Update Update No Change No Change from from...
Page 107: Pci/Ppc Contention Handling
Master anytime it is currently processing a transaction that must have control of the opposing bus before the transaction can be completed. The events that activate this signal are: Read cycle with no read data in the FIFO Non-posted write cycle Posted write cycle and FIFO full http://www.motorola.com/computer/literature 2-45...
Page 108 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller A simultaneous indication of a stall from both slaves means that a bridge lock has happened. To resolve this, one of the slaves must back out of its currently pending transaction. This will allow the other stalled slave to proceed with its transaction.
Page 109 Master will speculatively assert a request on the PCI bus. Sometime later when the processor comes back and retries the compelled cycle, the results of the PCI Master holding will increase the chance of the processor successfully completing its cycle. http://www.motorola.com/computer/literature 2-47...
Page 110: Transaction Ordering
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI speculative requesting will only be effective if the PCI arbiter will at least some times consider the PHB to be a higher priority master than the master performing the PPC60x bound write cycles. The PCI Master obeys the PCI specification for benign requests and will unconditionally remove a speculative request after 16 clocks.
Page 111: Phb Hardware Configuration
Hawk has the ability to perform custom hardware configuration to accommodate different system requirements. The PHB has several functions that may be optionally enabled or disabled using passive hardware external to Hawk. The selection process occurs at the first rising http://www.motorola.com/computer/literature 2-49...
Page 112: Table 2-15. Phb Hardware Configuration
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller edge of CLK after RST_ has been released. All of the sampled pins are cascaded with several layers of registers to eliminate problems with hold time. Table 2-15 summarizes the hardware configuration options that relate to the PHB.
Page 113: Multi-Processor Interrupt Controller (Mpic)
External interrupt 0 can be either level or edge activated with either polarity. The Hawk internal error interrupt request is an active low level sensitive interrupt. The Interprocessor and timers interrupts are event activated. http://www.motorola.com/computer/literature 2-51...
Page 114: External Interrupt Interface
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller If the OPIC bit (refer to the General Control-Status/Feature Registers section for more information) is enabled, the Hawk detected errors will be passed on to MPIC. If the OPIC bit is disabled, Hawk detected errors are passed directly to the processor 0 interrupt pin.
Page 115: Csr's Readability
15 is the highest. In order for delivery of an interrupt to take place, the priority of the source must be greater than that of the destination processor. Therefore, setting a source priority to zero inhibits that interrupt. http://www.motorola.com/computer/literature 2-53...
Page 116: Processor's Current Task Priority
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Processor’s Current Task Priority Each processor has a task priority register which is set by system software to indicate the relative importance of the task running on that processor. The processor will not receive interrupts with a priority level equal to or lower than its current task priority.
Page 117: Interprocessor Interrupts (Ipi)
Hawk ASIC. Presumably this signal will be connected to an externally sourced interrupt input of an MPIC controller of a different device. Since the MPIC specification defines external I/O interrupts to operate in the distributed mode, the delivery mode of this error interrupt should be consistent. http://www.motorola.com/computer/literature 2-55...
Page 118: Timers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timers There is a divide by eight pre scaler which is synchronized to the PCI clock. The output of the pre scaler enables the decrement of the four timers. The timers may be used for system timing or to generate periodic interrupts.
Page 119: Block Diagram Description
This is an arbitrary choice. Block Diagram Description The description of the MPIC block diagram shown in Figure 2-9 focuses on the theory of operation for the interrupt delivery logic. http://www.motorola.com/computer/literature 2-57...
Page 120: Figure 2-9. Mpic Block Diagram
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Int. signals Program Visible Registers Interrupt Interrupt Selector_1 Selector_0 IRR_1 IRR_0 ISR_1 ISR_0 Interrupt Router INT 1 INT 0 Figure 2-9. MPIC Block Diagram 2-58 Computer Group Literature Center Web Site...
Page 121: Program Visible Registers
The IS will resolve an interrupt request in two PHB clock ticks. The IS also receives a second set of inputs from the ISR. During the End Of Interrupt cycle, these inputs are used to select which bits are to be cleared in the ISR. http://www.motorola.com/computer/literature 2-59...
Page 122: Interrupt Request Register (Irr)
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Interrupt Request Register (IRR) There is a Interrupt Request Register (IRR) for each processor. The IRR always passes the output of the IS except during Interrupt Acknowledge cycles. This guarantees that the vector which is read from the Interrupt Acknowledge Register does not change due to the arrival of a higher priority interrupt.
Page 123 There is a possibility for a priority tie between the two processors when resolving external interrupts. In that case, the interrupt will be delivered to processor 0 or processor 1 as determined by the TIE mode bit. This case is not defined in the above rule set. http://www.motorola.com/computer/literature 2-61...
Page 124: Programming Notes
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Programming Notes External Interrupt Service The following summarizes how an external interrupt is serviced: An external interrupt occurs. The processor state is saved in the machine status save/restore registers. A new value is loaded into the Machine State Register (MSR).
Page 125: Reset State
All interrupt source priorities set to zero. All interrupt source mask bits set to a one. All interrupt source activity bits cleared. Processor Init Register is cleared. All counters stopped and interrupts disabled. Controller mode set to 8259 pass-through. http://www.motorola.com/computer/literature 2-63...
Page 126: Operation
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Operation Interprocessor Interrupts Four interprocessor interrupt (IPI) channels are provided for use by all processors. During system initialization the IPI vector/priority registers for each channel should be programmed to set the priority and vector returned for each IPI event.
Page 127: Eoi Register
This value is also used in determining the destination for interrupts which are delivered using the distributed deliver mode. http://www.motorola.com/computer/literature 2-65...
Page 128: Architectural Notes
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Architectural Notes The hardware and software overhead required to update the task priority register synchronously with instruction execution may far outweigh the anticipated benefits of the task priority register. To minimize this overhead, the interrupt controller architecture should allow the task priority register to be updated asynchronously with respect to instruction execution.
Page 129: Registers
PPC registers of PHB within this document are made with respect to the base address $FEFF0000. The following conventions are used in the Hawk register charts: Read Only field. Read/Write field. Writing a ONE to this field sets this field. Writing a ONE to this field clears this field. http://www.motorola.com/computer/literature 2-67...
Page 130: Ppc Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Registers The PPC register map of the PHB is shown in Table 2-16. Table 2-16. PPC Register Map for PHB Bit ---> 0 1 2 3 4 5 6 7 8 9 $FEFF0000 VENID DEVID...
Page 131 0 1 2 3 4 5 6 7 8 9 $FEFF0048 XSADD1 $FEFF004C XSOFF1 XSATT1 $FEFF0050 XSADD2 $FEFF0054 XSOFF2 XSATT2 $FEFF0058 XSADD3 $FEFF005C XSOFF3 XSATT3 $FEFF0060 WDT1CNTL $FEFF0064 WDT1STAT $FFEF0068 WDT2CNTL $FEFF006C WDT2STAT $FEFF0070 GPREG0(Upper) $FEFF0074 GPREG0(Lower) $FEFF0078 GPREG1(Upper) $FEFF007C GPREG1(Lower) http://www.motorola.com/computer/literature 2-69...
Page 132: Vendor Id/Device Id Registers
Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola and is hardwired as a read-only value. This register is duplicated in the PCI Configuration Registers.
Page 133: General Control-Status/Feature Registers
PPC Master continually requests the PPC bus for the entire duration of each transfer. If Bus Hog is not enabled, the PPC master requests the bus in a normal manner. Refer to the section titled Master for more information. http://www.motorola.com/computer/literature 2-71...
Page 134 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller XFBR PPC Flush Before Read. If set, the PHB will guarantee that all PCI initiated posted write transactions will be completed before any PPC-initiated read transactions will be allowed to complete. When XFBR is clear, there is no correlation between these transaction types and their order of completion.
Page 135: Ppc Arbiter/Pci Arbiter Control Registers
The encoding of this field is shown in the table below. FBR/FSR/FBW/FSW Effects on Bus Pipelining None None Flatten always Flatten if switching masters http://www.motorola.com/computer/literature 2-73...
Page 136 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Priority. If set, the PPC Arbiter will impose a rotating between CPU0 grants. If cleared, a fixed priority will be established between CPU0 and CPU1 grants, with CPU0 having a higher priority than CPU1. PRKx Parking.
Page 137 PARB3 -> PARB2 -> PARB1 -> PARB0 -> HAWK -> PARB6 -> PARB5 -> PARB4 PARB4 -> PARB3 -> PARB2 -> PARB1 -> PARB0 -> HAWK -> PARB6 -> PARB5 PARB5 -> PARB4 -> PARB3 -> PARB2 -> PARB1 -> PARB0 -> HAWK -> PARB6 http://www.motorola.com/computer/literature 2-75...
Page 138 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When using the mixed priority scheme, the encoding of this field is shown in the following table. HIER Priority ordering, highest to lowest Group 1 -> Group 2 -> Group 3 -> Group 4 Group 4 ->...
Page 139: Hardware Control-Status/Prescaler Adjust Register
Speculative PCI Request. If set, the PHB PCI Master will perform speculative PCI requesting when a PCI bound transaction has been retried due to bridge lock resolution. If cleared, the PCI Master will only request the PCI bus when a transaction is pending within the PHB FIFOs. http://www.motorola.com/computer/literature 2-77...
Page 140 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller WLRTx Write Lock Resolution Threshold. This field is used by the PHB to determine a PPC bound write FIFO threshold at which a bridge lock resolution will create a retry on a pending PCI bound transaction.
Page 141: Ppc Error Test/Error Enable Register
The Error Enable Register (EENAB) controls how the PHB is to respond to the detection of various errors. In particular, each error type can uniquely be programmed to generate a machine check, generate an interrupt, generate both, or generate neither. The bits within the ETEST are defined as follows: http://www.motorola.com/computer/literature 2-79...
Page 142 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller DFLT Default PPC Master ID. This bit determines which MCHK_ pin will be asserted for error conditions in which the PPC Master ID cannot be determined or the PHB was the PPC Master. For example, in the event of a PCI parity error for a transaction in which the PHB’s PCI Master was not involved, the PPC Master ID cannot be determined.
Page 143 PCI Master Received Target Abort Interrupt Enable. When this bit is set, the PRTA bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller. When this bit is clear, no interrupt will be asserted. http://www.motorola.com/computer/literature 2-81...
Page 144: Ppc Error Status Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Error Status Register The Error Status Register (ESTAT) provides an array of status bits pertaining to the various errors that the PHB can detect. The bits within the ESTAT are defined in the following paragraphs. Address $FEFF0024 0 1 2 3 4 5 6 7 8 9...
Page 145 MCHK to the master designated by the XID field in the EATTR register. When the PRTAI bit in the EENAB register is set, the assertion of this bit will assert an interrupt through the MPIC. http://www.motorola.com/computer/literature 2-83...
Page 146: Ppc Error Address Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Error Address Register The Error Address Register (EADDR) captures addressing information on the various errors that the PHB can detect. The register captures the PPC address when the XBTO bit is set in the ESTAT register. The register captures the PCI address when the PSMA or PRTA bits are set in the ESTAT register.
Page 147: Ppc Error Attribute Register
TSIZx Transfer Size. This field contains the transfer size of the PPC transfer in which the error occurred. Transfer Type. This field contains the transfer type of the PPC transfer in which the error occurred. http://www.motorola.com/computer/literature 2-85...
Page 148 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller If the PSMA or PRTA bit are set, the register is defined by the following table: Address $FEFF002C 0 1 2 3 4 5 6 7 8 9 Name EATTR Operation Reset Write Post Completion.
Page 149: Pci Interrupt Acknowledge Register
PCI interrupt acknowledge cycle, the PHB will present the resulting vector information obtained from the PCI bus as read data. Address $FEFF0030 0 1 2 3 4 5 6 7 8 9 Name PIACK Operation Reset $00000000 http://www.motorola.com/computer/literature 2-87...
Page 150: Ppc Slave Address (0,1 And 2) Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Slave Address (0,1 and 2) Registers The PPC Slave Address Registers (XSADD0, XSADD1, and XSADD2) contains address information associated with the mapping of PPC memory space to PCI memory I/O space. The fields within the XSADDx registers are defined as follows: Address XSADD0 - $FEFF0040...
Page 151: Ppc Slave Offset/Attribute (0, 1 And 2) Registers
Read Enable. If set, the corresponding PPC Slave is enabled for read transactions. Write Enable. If set, the corresponding PPC Slave is enabled for write transactions. WPEN Write Post Enable. If set, write posting is enable for the corresponding PPC Slave. http://www.motorola.com/computer/literature 2-89...
Page 152: Ppc Slave Address (3) Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI Memory Cycle. If set, the corresponding PPC Slave will generate transfers to or from PCI memory space. When clear, the corresponding PPC Slave will generate transfers to or from PCI I/O space using the addressing mode defined by the IOM field.
Page 153: Ppc Slave Offset/Attribute (3) Registers
PCI address used for transfers from the PPC bus to PCI. This offset allows PCI resources to reside at addresses that would not normally be visible from the PPC bus. It is initialized to $8000 to facilitate a zero based access to PCI space. http://www.motorola.com/computer/literature 2-91...
Page 154: Wdtxcntl Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PPC Slave Attributes Register 3 (XSATT3) contains attribute information associated with the mapping of PPC memory space to PCI I/O space. The bits within the XSATT3 register are defined as follows: Read Enable.
Page 155 The following table shows the different options associated with this bit. Timer Resolution Approximate Max Time 0000 1 us 64 msec 0001 2 us 128 msec 0010 4 us 256 msec 0011 8 us 512 msec http://www.motorola.com/computer/literature 2-93...
Page 156 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timer Resolution Approximate Max Time 0100 16 us 1 sec 0101 32 us 2 sec 0110 64 us 4 sec 0111 128 us 8 sec 1000 256 us 16 sec 1001 512 us 32 sec 1010 1024 us...
Page 157 FEFF0068 0088FFFF 00000000 03FE4000 00000000 ...@..FEFF0078 00000000 FFFFFFFE FFFFFFFF FFFFFFFF ....PPC6-Bug>md feff006c FEFF006C 00000000 03FE4000 00000000 00000000 ..@..FEFF007C FFFFFFFE FFFFFFFF FFFFFFFF FFFFFFFF ....PPC6-Bug>md feff0068 FEFF0068 0088FFFF 00000000 03FE4000 00000000 ...@..FEFF0078 00000000 FFFFFFFE FFFFFFFF FFFFFFFF ....PPC6-Bug> http://www.motorola.com/computer/literature 2-95...
Page 158: Wdtxstat Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller WDTxSTAT Registers Address WDT1STAT - $FEFF0064 WDT2STAT - $FEFF006C WDTxSTAT Name COUNT Operation Reset The Watchdog Timer Status Registers (WDT1STAT and WDT2STAT) are used to provide status information from the watchdog timer functions within the PHB.
Page 159: Pci Registers
Table 2-17. PCI Configuration Register <--- Bit 0 9 8 7 6 5 4 3 2 1 0 DEVID VENID STATUS COMMAND CLASS REVID HEADER MIBAR MMBAR $18 - $7C PSADD0 PSOFF0 PSATT0 PSADD1 PSOFF1 PSATT1 PSADD2 PSOFF2 PSATT2 PSADD3 PSOFF3 PSATT3 http://www.motorola.com/computer/literature 2-97...
Page 160: Vendor Id/ Device Id Registers
VENID Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the PPC Registers. DEVID Device ID. This register identifies the particular device.
Page 161: Pci Command/ Status Registers
SERR System Error Enable. This bit enables the SERR_ output pin. If clear, the PHB will never drive SERR_. If set, the PHB will drive SERR_ active when a system error is detected. http://www.motorola.com/computer/literature 2-99...
Page 162 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The Status Register (STATUS) is used to record information for PCI bus related events. The bits within the STATUS register are defined as follows: P66M PCI66 MHz. This bit indicates the PHB is capable of supporting a 66.67 MHz PCI bus.
Page 163: Revision Id/ Class Code Registers
PCI Bridge Device Subclass Code PCI Host Bridge Program Class Code Not Used Header Type Register Offset Name HEADER Operation Reset The Header Type Register (Header) identifies the PHB as the following: Header Type: $00 - Single Function Configuration Header http://www.motorola.com/computer/literature 2-101...
Page 164: Mpic I/O Base Address Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC I/O Base Address Register Offset 0 9 8 7 6 5 4 3 2 1 0 Name MIBAR BASE Operation Reset $0000 $0000 The MPIC I/O Base Address Register (MIBAR) controls the mapping of the MPIC control registers in PCI I/O space.
Page 165: Pci Slave Address (0,1,2, And 3) Registers
PCI Slave Address (0,1,2, and 3) Registers Offset PSADD0 - $80 PSADD1 - $88 PSADD2 - $90 PSADD3 - $98 0 9 8 7 6 5 4 3 2 1 0 Name PSADDx START Operation Reset $0000 $0000 http://www.motorola.com/computer/literature 2-103...
Page 166: Pci Slave Attribute/ Offset (0,1,2 And 3) Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave Address Registers (PSADDx) contain address information associated with the mapping of PCI memory space to PPC memory space. The fields within the PSADDx registers are defined as follows: START Start Address.
Page 167 Read Any FIFO Threshold. This field is used by the PHB to determine a FIFO threshold at which to continue prefetching data from local memory during PCI read and read line transactions. This threshold applies to subsequent prefetch reads since all initial prefetch reads http://www.motorola.com/computer/literature 2-105...
Page 168: Config_Address Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller will be four cache lines. This field is only applicable if read-ahead has been enabled. The encoding of this field is shown in the table above. WXFT Write FIFO Threshold 4 Cache lines 3 Cache lines 2 Cache lines 1 Cache lines...
Page 169 0 1 2 3 4 5 6 7 8 9 Name CONFIG_ADDRESS Operation Reset Perspective from the PPC bus in Little Endian mode: Offset $CFC $CFD $CFE $CFF Bit (DL) 0 1 2 3 4 5 6 7 8 9 Name CONFIG_ADDRESS Operation Reset http://www.motorola.com/computer/literature 2-107...
Page 170 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The register fields are defined as follows: Register Number. Configuration Cycles: Identifies a target double word within a target’s configuration space. This field is copied to the PCI AD bus during the address phase of a Configuration cycle.
Page 171: Config_Data Register
Perspective from the PPC bus in Little Endian mode: Offset $CF8 $CF9 $CFA $CFB Bit (DH) 0 1 2 3 4 5 6 7 8 9 Name CONFIG_DATA Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation Reset http://www.motorola.com/computer/literature 2-109...
Page 172: Mpic Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC Registers The following conventions are used in the Hawk register charts: R - Read Only field. R/W - Read/Write field. S - Writing a ONE to this field sets this field. C - Writing a ONE to this field clears this field.
Page 173: Table 2-19. Mpic Register Map
INT. SRC. 1 DESTINATION REGISTER $10030 INT. SRC. 2 VECTOR-PRIORITY REGISTER $10040 INT. SRC. 2 DESTINATION REGISTER $10050 INT. SRC. 3 VECTOR-PRIORITY REGISTER $10060 INT. SRC. 3 DESTINATION REGISTER $10070 INT. SRC. 4 VECTOR-PRIORITY REGISTER $10080 INT. SRC. 4 DESTINATION REGISTER $10090 http://www.motorola.com/computer/literature 2-111...
Page 174 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-19. MPIC Register Map (Continued) 0 9 8 7 6 5 4 3 2 1 0 INT. SRC. 5 VECTOR-PRIORITY REGISTER $100a0 INT. SRC. 5 DESTINATION REGISTER $100b0 INT. SRC. 6 VECTOR-PRIORITY REGISTER $100c0 INT.
Page 175 $21070 CURRENT TASK PRIORITY REGISTER PROC. 1 $21080 IACK REGISTER $210a0 EOI REGISTER $210b0 Feature Reporting Register Offset $01000 0 9 8 7 6 5 4 3 2 1 0 Name FEATURE REPORTING NIRQ NCPU Operation Reset $00F http://www.motorola.com/computer/literature 2-113...
Page 176 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller NIRQ NUMBER OF IRQs. The number of the highest external IRQ source supported. The IPI, Timer, and PHB Detected Error interrupts are excluded from this count. NCPU NUMBER OF CPUs. The number of the highest physical CPU supported.
Page 177: Table 2-20. Cascade Mode Encoding
When this register bit is set to 0, a tie in external interrupt processing will always go to processor 0 (Mode used on Version $02 of MPIC). Table 2-21. Tie Mode Encoding Mode Processor 0 always selected Swap between Processor’s http://www.motorola.com/computer/literature 2-115...
Page 178: Vendor Identification Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Vendor Identification Register Offset $01080 0 9 8 7 6 5 4 3 2 1 0 Name VENDOR IDENTIFICATION Operation Reset There are two fields in the Vendor Identification Register which are not defined for the MPIC implementation but are defined in the MPIC specification.
Page 179: Ipi Vector/Priority Registers
PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-117...
Page 180: Spurious Vector Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Spurious Vector Register Offset $010E0 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation Reset VECTOR This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch. Timer Frequency Register Offset $010F0...
Page 181: Timer Current Count Registers
Count Inhibit bit is the Base Count Register is zero. When the timer counts down to zero, the Current Count register is reloaded from the Base Count register and the timer’s interrupt becomes pending in MPIC processing. http://www.motorola.com/computer/literature 2-119...
Page 182: Timer Basecount Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timer Basecount Registers Offset Timer 0 - $01110 Timer 1 - $01150 Timer 2 - $01190 Timer 3 - $011D0 0 9 8 7 6 5 4 3 2 1 0 Name TIMER BASECOUNT Operation Reset...
Page 183: Timer Vector/Priority Registers
PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-121...
Page 184: Timer Destination Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timer Destination Registers Offset Timer 0 - $01130 Timer 1 - $01170 Timer 2 - $011B0 Timer 3 - $011F0 0 9 8 7 6 5 4 3 2 1 0 Name TIMER DESTINATION Operation Reset...
Page 185 PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-123...
Page 186: External Source Destination Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller External Source Destination Registers Offset Int Src 0 - $10010 Int Src 1-> Int Src 15 - $10030 -> $101F0 0 9 8 7 6 5 4 3 2 1 0 Name EXTERNAL SOURCE DESTINATION Operation Reset...
Page 187: Hawk Internal Error Interrupt Vector/Priority Register
PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-125...
Page 188: Hawk Internal Error Interrupt Destination Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Hawk Internal Error Interrupt Destination Register Offset $10210 0 9 8 7 6 5 4 3 2 1 0 Name HAWK INTERNAL ERROR INTERRUPT DESTINATION Operation Reset This register indicates the possible destinations for the Hawk internal error interrupt source.
Page 189: Current Task Priority Registers
$FF hex. The associated bit in the Interrupt Pending Register is cleared. Reading this register will update the In-Service register. VECTOR Vector. This vector is returned when the Interrupt Acknowledge register is read. http://www.motorola.com/computer/literature 2-127...
Page 190: End-Of-Interrupt Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller End-of-Interrupt Registers Offset Processor 0 $200B0 Processor 1 $210B0 0 9 8 7 6 5 4 3 2 1 0 Name Operation Reset END OF INTERRUPT. There is one EOI register per processor.
Page 191: Introduction
3System Memory Controller (SMC) Introduction The SMC in the Hawk ASIC is equivalent to the former Falcon Pair portion of a Falcon/Raven chipset. The SMC has interfaces between the PPC60x bus and SDRAM, ROM/Flash, and its Control and Status Register sets (CSR).
Page 192: Block Diagrams
System Memory Controller (SMC) ROM/Flash Interface – Two blocks with each block being 16 or 64 bits wide. – Programmable access time on a per-block basis. C master interface. External status/control register support Block Diagrams Figure 3-1 depicts a Hawk as it would be connected with SDRAMs in a system.
Page 193: Figure 3-2. Hawk's System Memory Controller Internal Data Paths
Block Diagrams SDRAM PowerPC Side Side (8 Bits) Latched D (64 Bits) (64 Bits) (8 Bits) (8 Bits) (8 Bits) Uncorrected Data (64 Bits) Figure 3-2. Hawk’s System Memory Controller Internal Data Paths http://www.motorola.com/computer/literature...
Page 194: Figure 3-3. Overall Sdram Connections (4 Blocks Using Register Buffers)
System Memory Controller (SMC) D0/D1_CS_ C0/C1_CS_ B0/B1_CS_ A0/A1_CS_ BA,RA,RAS_, CAS_,WE_,DQM RD0-63 CKD0-7 SDRAM SDRAM SDRAM SDRAM BLOCK A BLOCK B BLOCK C BLOCK D Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers) Computer Group Literature Center Web Site...
Page 195: Figure 3-4. Hawk's System Memory Controller Block Diagram
INTERFACE CONTROL REFRESHER MEM Addr PPC60x Attr PPC60x SDRAM /SCRUBBER ADDRESS ADDRESS ARBITER DECODER MULTIPLEXOR PPC60x Addr STATUS SDRAM /CONTROL ERROR REGISTERS JTAG LOGGER INTERFACE MEM Data PPC60x Data DATA MULTIPLEXOR Figure 3-4. Hawk’s System Memory Controller Block Diagram http://www.motorola.com/computer/literature...
Page 196: Functional Description
System Memory Controller (SMC) Functional Description The following sections describe the logical function of the SMC. The SMC has interfaces between the PowerPC bus and SDRAM, ROM/Flash, and its Control and Status Register sets (CSR). SDRAM Accesses Four-beat Reads/Writes The SMC performs best when doing bursting (4-beat accesses). This is made possible by the burst nature of synchronous DRAMs.
Page 197: Page Holding
1-1-1 half of the time and 3- SDRAM Bank Active - Page Hit 1-1-1 the other half. 4-Beat Write after idle, 4-1-1-1 SDRAM Bank Active or Inactive 4-Beat Write after 4-Beat Write, 6-1-1-1 SDRAM Bank Active - Page Miss http://www.motorola.com/computer/literature...
Page 198 System Memory Controller (SMC) Table 3-1. 60 x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAMs (CAS_latency of 2) (Continued) Access Type Access Time Comments 4-Beat Write after 4-Beat Write, 3-1-1-1 3-1-1-1 for the second burst write after idle.
Page 199: Sdram Organization
If the data transfer will be a write, the SMC begins latching data from the PowerPC data bus as soon as any previously latched data is no longer needed and the PPC60x data bus is available. http://www.motorola.com/computer/literature...
Page 200: Ppc60X Data Parity
System Memory Controller (SMC) PPC60x Data Parity The Hawk has 8 DP pins for generating and checking PPC60x data bus parity. During read cycles that access the SMC, the Hawk generates the correct value on DP0-DP7 so that each data byte lane along with its corresponding DP signal has odd parity.
Page 201: Cache Coherency
When the PPC60x bus master requests a single-beat write to SDRAM, the SMC performs a full width read cycle to SDRAM, merges in the appropriate PPC60x bus write data, and writes full width back to SDRAM. http://www.motorola.com/computer/literature 3-11...
Page 202: Error Reporting
System Memory Controller (SMC) Error Reporting The SMC checks data from the SDRAM during single- and four-beat reads, during single-beat writes, and during scrubs. Table 3-2 shows the actions it takes for different errors during these accesses 60x. Note that the SMC does not assert TEA_ on double-bit errors. In fact, the SMC does not have a TEA_ signal pin and it assumes that the system does not implement TEA_.
Page 203: Error Logging
The logging of errors that occur during scrub can be enabled/disabled in software. Refer to the Error Logger Register section in this chapter for more information. http://www.motorola.com/computer/literature 3-13...
Page 204: Rom/Flash Interface
System Memory Controller (SMC) ROM/Flash Interface The SMC provides the interface for two blocks of ROM/Flash. Each block provides addressing and control for up to 64MB. Note that no ECC error checking is provided for the ROM/Flash. The ROM/Flash interface allows each block to be individually configured by jumpers and/or by software as follows: 1.
Page 205 In order to place code correctly in the ROM/Flash devices, address mapping information is required. Table 3-3 shows how PPC60x addresses map to the ROM/Flash addresses when ROM/Flash is 16 bits wide. Table shows how they map when Flash is 64 bits wide. http://www.motorola.com/computer/literature 3-15...
Page 206: Table 3-3. Ppc60X To Rom/Flash (16 Bit Width)
System Memory Controller (SMC) Table 3-3. PPC60x to ROM/Flash (16 Bit Width) Address Mapping PPC60x A0-A31 ROM/Flash A22-A0 ROM/Flash Device Selected $XX000000 $000000 Upper $XX000001 $000001 Upper $XX000002 $000002 Upper $XX000003 $000003 Upper $XX000004 $000000 Lower $XX000005 $000001 Lower $XX000006 $000002 Lower $XX000007...
Page 207: Table 3-4. Ppc60X To Rom/Flash (64 Bit Width) Address Mapping
$000001 Lower $X000000E $000001 Lower $X000000F $000001 Lower $X3FFFFF0 $7FFFFE Upper $X3FFFFF1 $7FFFFE Upper $X3FFFFF2 $7FFFFE Upper $X3FFFFF3 $7FFFFE Upper $X3FFFFF4 $7FFFFE Lower $X3FFFFF5 $7FFFFE Lower $X3FFFFF6 $7FFFFE Lower $X3FFFFF7 $7FFFFE Lower $X3FFFFF8 $7FFFFF Upper $X3FFFFF9 $7FFFFF Upper http://www.motorola.com/computer/literature 3-17...
Page 208 System Memory Controller (SMC) Table 3-4. PPC60x to ROM/Flash (64 Bit Width) Address Mapping (Continued) PPC60x A0-A31 ROM/Flash A22-A0 ROM/Flash Device Selected $X3FFFFFA $7FFFFF Upper $X3FFFFFB $7FFFFF Upper $X3FFFFFC $7FFFFF Lower $X3FFFFFD $7FFFFF Lower $X3FFFFFE $7FFFFF Lower $X3FFFFFF $7FFFFF Lower 3-18 Computer Group Literature Center Web Site...
Page 209: Rom/Flash Speeds
4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes) 1-Beat Write Note The information in Table 3-5 applies to access timing when configured for devices with an access time equal to 12 clock periods. http://www.motorola.com/computer/literature 3-19...
Page 210: Table 3-6. Ppc60X Bus To Rom/Flash Access Timing (80Ns @ 100 Mhz)
System Memory Controller (SMC) Table 3-6. PPC60x Bus to ROM/Flash Access Timing (80ns @ 100 MHz) CLOCK PERIODS REQUIRED FOR: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat ACCESS TYPE Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4-Beat Read...
Page 211: Table 3-8. Ppc60X Bus To Rom/Flash Access Timing (30Ns @ 100 Mhz)
4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes) 1-Beat Write Note The information in Table 3-8 applies to access timing when configured for devices with an access time equal to 3 clock periods. http://www.motorola.com/computer/literature 3-21...
Page 212: I2C Interface
System Memory Controller (SMC) C Interface The ASIC has an I C (Inter-Integrated Circuit) two-wire serial interface bus: Serial Clock Line (SCL) and Serial Data Line (SDA). This interface has master-only capability and may be used to communicate the configuration information to a slave I C device such as serial EEPROM.
Page 213: I2C Byte Write
The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master’s possession of the I C bus. Figure 3-5 shows the suggested software flow diagram for programming the I C byte write operation. http://www.motorola.com/computer/literature 3-23...
Page 214: Figure 3-5. Programming Sequence For I2C Byte Write
System Memory Controller (SMC) DEVICE ADDR WORD ADDR DATA START STOP ACK from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG CMPLT=ACKIN=1? LOAD “WORD ADDR”...
Page 215 _cmplt bit for the operation-complete status. The stop sequence will relinquish the ASIC master’s possession of the I C bus. Figure 3-6 shows the suggested software flow diagram for programming the I C random read operation. http://www.motorola.com/computer/literature 3-25...
Page 216 System Memory Controller (SMC) DEVICE ADDR WORD ADDR x DEVICE ADDR START START DATA x STOP ACK and DATA from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG...
Page 217: I2C Current Address Read
The stop sequence will relinquish the ASIC master’s possession of the I C bus. Figure 3-7 shows the suggested software flow diagram for programming the I C current address read operation. http://www.motorola.com/computer/literature 3-27...
Page 218 System Memory Controller (SMC) DATA of (last ADDR+1) DEVICE ADDR START STOP ACK and DATA from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+RD BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG CMPLT=ACKIN=1?
Page 219: I2C
The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master’s possession of the I C bus. Figure 3-8 shows the suggested software flow diagram for programming the I C page write operation. http://www.motorola.com/computer/literature 3-29...
Page 220 System Memory Controller (SMC) DEVICE ADDR WORD ADDR 1 DATA 1 DATA n START STOP ACK from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG CMPLT=ACKIN=1?
Page 221: I2C Sequential Read
C Status Register) and the i2_cmplt bit has also been tested for proper status, the I C master controller responds with an acknowledge and the system software may then read the data by polling the I C Receiver Data Register. http://www.motorola.com/computer/literature 3-31...
Page 222 System Memory Controller (SMC) As long as the slave device receives an acknowledge, it will continue to increment the word address and serially clock out sequential data words. The I C sequential read operation is terminated when the I C master controller does not respond with an acknowledge.
Page 223 READ I C STATUS REG READ I C STATUS REG CMPLT=ACKIN=1? CMPLT=1? Stop condition should be generated to abort the transfer after a software wait loop (~1ms) has been expired Figure 3-9. Programming Sequence for I C Sequential Read http://www.motorola.com/computer/literature 3-33...
Page 224: Refresh/Scrub
System Memory Controller (SMC) Refresh/Scrub The SMC performs refresh by doing a burst of 4 CAS-Before-RAS (CBR) refresh cycles to each block of SDRAM once every 60 microseconds. It performs scrubs by replacing every 128th refresh burst with a read cycle to 8 bytes in each block of SDRAM.
Page 225: Chip Configuration
PPC60x data bus. CSR read accesses can have a size of 1, 2, 4, or 8 bytes with any alignment. CSR write accesses are restricted to a size of 1 or 4 bytes and they must be aligned. http://www.motorola.com/computer/literature 3-35...
Page 226: Register Summary
System Memory Controller (SMC) Register Summary Table 3-9 shows a summary of the internal and external register set. Table 3-9. Register Summary BIT # ----> FEF80000 VENDID DEVID REVID PU STAT FEF80008 RAM A RAM B RAM C RAM D FEF80010 FEF80018 RAM A BASE...
Page 227 RAM E RAM F RAM G RAM H FEF800C0 FEF800C8 RAM E BASE RAM F BASE RAM G BASE RAM H BASE FEF800D0 APE_TT APE_AP FEF800E0 FEF800E8 APE_A FEF80100 CTR32 FEF88300 FEF88000 EXTERNAL REGISTER SET FEF8FFF8 BIT # ----> http://www.motorola.com/computer/literature 3-37...
Page 228: Detailed Register Bit Descriptions
System Memory Controller (SMC) Notes 1. All empty bit fields are reserved and read as zeros. 2. All status bits are shown in italics. 3. All control bits are shown with underline. 4. All control-and-status bits are shown with italics and underline.
Page 229: Vendor/Device Register
Reset $1057 $4803 VENDID This read-only register contains the value $1057. It is the vendor number assigned to Motorola Inc. DEVID This read-only register contains the value $4803. It is the device number for the Hawk. Revision ID/General Control Register...
Page 230 System Memory Controller (SMC) Software should only set the tben_en bit when there is no external L2 cache connected to the I2clm_ pin and when there is no external register set. REVID The REVID bits are hard-wired to indicate the revision level of the SMC.
Page 231: Sdram Enable And Size Register (Blocks A, B, C, D)
SDRAM. Table 3-10 shows the block configuration assumed by the SMC for each value of ram siz0-ram siz3. Note that ram e/f/g/h size0-3 are located at $FEF800C0. They operate identically for blocks E-H as these bits do for blocks A-D. http://www.motorola.com/computer/literature 3-41...
Page 232: Table 3-10. Block_A/B/C/D/E/F/G/H Configurations
System Memory Controller (SMC) Table 3-10. Block_A/B/C/D/E/F/G/H Configurations ram a-h Component Number of Block SDRAM siz0-3 Configuration SDRAM SIZE Technology Components In the Block %0000 0MBytes %0001 4Mx16 32MBytes 64Mbit %0010 8Mx8 64MBytes 64Mbit %0011 8Mx16 64MBytes 128Mbit %0100 16Mx4 128MBytes 64Mbit %0101...
Page 233: Sdram Base Address Register (Blocks A/B/C/D)
E-H as these bits do for blocks A-D. Also note that the combination of RAM_X_BASE and ram_x_siz should never be programmed such that SDRAM responds at the same address as the CSR, ROM/Flash, External Register Set, or any other slave on the PowerPC bus. http://www.motorola.com/computer/literature 3-43...
Page 234: Clk Frequency Register
System Memory Controller (SMC) CLK Frequency Register Address $FEF80020 Name CLK FREQUENCY Operation READ/WRITE READ ZERO READ ZERO Reset 64 P CLK FREQUENCY These bits should be programmed with the hexadecimal value of the operating CLOCK frequency in MHz (i.e. $42 for 66 MHz).
Page 235: Ecc Control Register
PPC60x bus to access check-bit data rather than normal data. The data path used for reading and writing check bits is D0-D7. Each 8-bit check-bit location services 64 bits of normal data. Figure 3-10 shows the relationship between normal data and check-bit data. http://www.motorola.com/computer/literature 3-45...
Page 236: Figure 3-10. Read/Write Check-Bit Data Paths
System Memory Controller (SMC) Normal View of Data (rwcb=0) 64 bits Check-bit View (rwcb=1) Figure 3-10. Read/Write Check-bit Data Paths Note that if test software attempts to force a single-bit error to a location using the rwcb function, the scrubber may correct the location before the test software gets a chance to check for the single-bit error.
Page 237 When dpien is set, the logging of a PPC60x data parity error causes the int bit to be set if it is not already. When the int bit is set, the Hawk’s internal error interrupt is asserted. http://www.motorola.com/computer/literature 3-47...
Page 238 System Memory Controller (SMC) sien When sien is set, the logging of a single-bit error causes the int bit to be set if it is not already. When the int bit is set, the Hawk’s internal error interrupt is asserted. mien When mien is set, the logging of a non-correctable error causes the int bit to be set if it is not already.
Page 239: Error Logger Register
It is cleared by the logging of a single-bit error. It is undefined after power-up reset. The syndrome code is meaningless if its embt bit is set. http://www.motorola.com/computer/literature 3-49...
Page 240 System Memory Controller (SMC) esbt esbt is set by the logging of a single-bit error. It is cleared by the logging of a multiple-bit error. When the SMC logs a single-bit error, the syndrome code indicates which bit was in error. Refer to the section on SDRAM ECC Codes. ERR_SYNDROME ERR_SYNDROME reflects the syndrome value at the last logging of an error.
Page 241: Error_Address Register
Each time the SMC performs a refresh burst, the scrub prescale counter increments by one. When the scrub prescale counter reaches the value stored in this register, it clears and resumes counting starting at 0. http://www.motorola.com/computer/literature 3-51...
Page 242: Scrub Address Register
System Memory Controller (SMC) Note that when this register is all 0’s, the scrub prescale counter does not increment, disabling any scrubs from occurring. Since SCRUB_FREQUENCY is cleared to 0’s at power-up reset, scrubbing is disabled until software programs a non-zero value into it. Scrub Address Register Address $FEF80048...
Page 243: Rom A Base/Size Register
ROM/Flash being used for Block A. When rom_a_64 is cleared, Block A is 16 bits wide, where each half of SMC interfaces to 8 bits. When rom_a_64 is set, Block A is 64 bits wide, where http://www.motorola.com/computer/literature 3-53...
Page 244: Table 3-11. Rom Block A Size Encoding
System Memory Controller (SMC) each half of the SMC interfaces to 32 bits. rom_a_64 matches the value that was on the RD2 pin at power-up reset. It cannot be changed by software. rom a siz The rom a siz control bits are the size of ROM/Flash for Block A.
Page 245: Table 3-13. Read/Write To Rom/Flash
No Response write 4-byte Misaligned No Response write 4-byte Aligned No Response write 4-byte Aligned Normal termination, but no write to ROM/Flash write 4-byte Aligned Normal termination, write occurs to ROM/Flash write 2,3,5,6,7, No Response 8,32-byte read Normal Termination http://www.motorola.com/computer/literature 3-55...
Page 246: Rom B Base/Size Register
System Memory Controller (SMC) ROM B Base/Size Register Address $FEF80058 Name ROM B BASE Operation READ/WRITE READ ZERO Reset $FF4 PL Writes to this register must be enveloped by a period of time in which no accesses to ROM/Flash Block B, occur. A simple way to provide the envelope is to perform at least two accesses to this (or another of the SMC’s registers before and after the write).
Page 247: Table 3-14. Rom Block B Size Encoding
RD1 pin. rom b en When rom b en is set, accesses to Block B ROM/Flash in the address range selected by ROM B BASE are enabled. When rom b en is cleared they are disabled. http://www.motorola.com/computer/literature 3-57...
Page 248: Rom Speed Attributes Registers
System Memory Controller (SMC) rom b we When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is cleared, they are disabled. Refer back to Table 3-13 for more details. ROM Speed Attributes Registers Address $FEF80060 Name...
Page 249: Table 3-15. Rom Speed Bit Encodings
ROM/Flash, Bank B, occur. A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC’s registers before and after the write. http://www.motorola.com/computer/literature 3-59...
Page 250: Data Parity Error Log Register
System Memory Controller (SMC) Data Parity Error Log Register Address $FEF80068 Name GWDP DPE_DP Operation READ ONLY READ/WRITE Reset 0 PL dpelog dpelog is set when a parity error occurs on the PPC60x data bus during a PPC60x data cycle whose parity the SMC is qualified to check.
Page 251: Data Parity Error Address Register
DPE_DH is the value on the upper half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk. It is updated only when dpelog goes from 0 to 1. http://www.motorola.com/computer/literature 3-61...
Page 252: Data Parity Error Lower Data Register
System Memory Controller (SMC) Data Parity Error Lower Data Register Address $FEF80080 Name DPE_DL Operation READ ONLY Reset 0 PL DPE_DL DPE_DL is the value on the lower half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk.
Page 253 After the start sequence and the I C Transmitter Data Register contents have been transmitted, the I C master controller will automatically clear the i2_start bit and then set the i2_cmplt bit in the I C Status Register. http://www.motorola.com/computer/literature 3-63...
Page 254 System Memory Controller (SMC) i2_stop When set, the I C master controller generates a stop sequence on the I C bus on the next dummy write (data=don’t care) to the I C Transmitter Data Register and clears the i2_cmplt bit in the I C Status Register.
Page 255: I2C Transmitter Data Register
I Receiver Data Register. If a value is written to I2_DATAWR (data=don’t care) when the i2_stop and i2_enbl bits in the I Control Register are set, a stop sequence is generated. http://www.motorola.com/computer/literature 3-65...
Page 256: I2C Receiver Data Register
System Memory Controller (SMC) C Receiver Data Register Address $FEF800B0 Name I2_DATARD Operation READ ZERO READ ZERO READ ZERO READ Reset 0 PL I2_DATARD The I2_DATARD contains the receive byte for I C data transfers. During I C sequential read operation, the current receive byte must be read before any new one can be brough in.
Page 257: Sdram Base Address Register (Blocks E/F/G/H)
PowerPC60x address bits 0 - 7. For larger SDRAM sizes, the lower significant bits of RAM E/F/G/HBASE are ignored. This means that the block’s base address will always appear at an even multiple of its size. Remember that bit 0 is MSB. http://www.motorola.com/computer/literature 3-67...
Page 258: Sdram Speed Attributes Register
System Memory Controller (SMC) Note that RAM A/B/C/D BASE are located at $FEF80018 (refer to the section titled SDRAM Base Address Register (Blocks A/B/C/D) for more information). They operate the same for blocks A-D as these bits do for blocks E-H. Also note that the combination of RAM_X_BASE and ram_x_siz should never be programmed such that SDRAM responds at the same address as the CSR, ROM/Flash,...
Page 259: Table 3-16. Trc Encoding
%111 tras0,1 Together tras0,1 determine the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its tRAS parameter. These bits are encoded as follows: Table 3-17. tras Encoding tras0,1 Minimum Clocks for tras http://www.motorola.com/computer/literature 3-69...
Page 260: Address Parity Error Log Register
System Memory Controller (SMC) swr_dpl swr_dpl causes the SMC to always wait until four clocks after the write command portion of a single write before allowing a precharge to occur. This function may not be required. If such is the case, swr_dpl can be cleared by software. tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Tdp parameter.
Page 261: Address Parity Error Address Register
Name APE_A Operation READ ONLY Reset 0 PL APE_A APE_A is the address of the last PPC60x address bus parity error that was logged by the Hawk. It is updated only when apelog goes from 0 to 1. http://www.motorola.com/computer/literature 3-71...
Page 262: 32-Bit Counter
System Memory Controller (SMC) 32-Bit Counter Address $FEF80100 Name CTR32 Operation READ/WRITE Reset 0 PL CTR32 CTR32 is a 32-bit, free-running counter that increments once per microsecond if the CLK_FREQUENCY register has been programmed properly. Notice that CTR32 is cleared by power-up and local reset. Note When the system clock is a fractional frequency, such as 66.67 MHz, CTR32 will count at a fractional amount faster or...
Page 263: Tben Register
When the tben_en bit is set, the L2CLM_ input pin becomes the P1_TBEN output pin and it tracks the value on p1_tben. When p1_tben is 0, the P1_TBEN pin is low and when p1_tben is 1, the P1_TBEN pin is high. http://www.motorola.com/computer/literature 3-73...
Page 264: Software Considerations
System Memory Controller (SMC) When the tben_en bit is cleared, p1_tben has no effect on any pin. p0_tben When the tben_en bit is set, the ERCS_ output pin becomes the P1_TBEN output pin and it tracks the value on p0_tben. When p0_tben is 0, the P0_TBEN pin is low and when p1_tben is 1, the P0_TBEN pin is high.
Page 265: Initializing Sdram Related Control Registers
SDRAM device data from serial EEPROM’s. Once software knows the SDRAM speed parameters for all blocks, it should discontinue accessing SDRAM for at least one refresh period before and after it programs the SDRAM speed attribute bits. http://www.motorola.com/computer/literature 3-75...
Page 266: Sdram Size
System Memory Controller (SMC) SDRAM Size The SDRAM size control bits come up from power-up reset cleared to zero. Once software has determined the correct size for an SDRAM block, it should set the block’s size bits to match. The value programmed into the size bits tells the Hawk how big the block is (for map decoding), and how to translate that block’s 60x addresses to SDRAM addresses.
Page 267: Sdram Control Registers Initialization Example
Check SPD byte 18 to determine which CAS latencies are supported. b. If a CAS latency of 2 is supported, then go to Step 3. Otherwise, a CAS latency of 3 is all that is supported for this block. http://www.motorola.com/computer/literature 3-77...
Page 268: Table 3-18. Deriving Tras, Trp, Trcd And Trc Control Bit Values From Spd Information
System Memory Controller (SMC) c. If a CAS latency of 2 is supported, check SPD byte 23 to determine the CAS_latency _2 cycle time. If the CAS_latency_2 cycle time is less than or equal to the period of the system clock then this block can operate with a CAS latency of 2.
Page 269 9.0 < tRC_CLK <= 10.0 trc =%010 tRP)/T bits 5,6,7 (SPD Bytes 10.0 < tRC_CLK <= trc =%011 30 and 27) (T = CLK Period (trc) 11.0 in nanoseconds) 11.0 < tRC_CLK illegal See Notes 7, 8 and 9 http://www.motorola.com/computer/literature 3-79...
Page 270 System Memory Controller (SMC) Notes 1. Use tRAS from the SDRAM block that has the slowest tRAS. 2. tRAS_CLK is tRAS expressed in CLK periods. 3. Use tRP from the SDRAM block that has the slowest tRP. 4. tRP_CLK is tRP expressed in CLK periods. 5.
Page 271: Table 3-19. Programming Sdram Siz Bits
32-bit counter to increment at least 100 times. (Refer to the section titled “32-Bit Counter” for more information). Note that the refdis control bit must not be set in the ECC Control Register. http://www.motorola.com/computer/literature 3-81...
Page 272 System Memory Controller (SMC) 8. Now that at least one refresh has occurred since SDRAM was last accessed, it is okay to write to the SDRAM control registers. a. Program the SDRAM Speed Attributes Register using the information obtained in steps 3 and 4 and the fact that the swr_dp and tdp bits should be set to 1’s.
Page 273: Optional Method For Sizing Sdram
$00000000 - $20000000. (Refer to the section on ROM A Base/Size Register and ROM B Base/Size Register for more information.) g. Make sure that no other devices are set up to respond in the range $00000000 - $20000000. http://www.motorola.com/computer/literature 3-83...
Page 274 System Memory Controller (SMC) 2. For each of the Blocks A through H: a. Set the block’s base address to $00000000. Refer to the sections titled SDRAM Base Address Register (Blocks A/B/C/D) and SDRAM Enable and Size Register (Blocks E,F,G,H). b.
Page 275: Table 3-20. Address Lists For Different Block Size Checks
2. 8Mx16 and 8Mx8 are the same. The same idea that applies to 16Mx8 and 16Mx4 applies to them. 3. This needed only to check for non-zero size. 3. Wait enough time to allow at least 1 SDRAM refresh to occur before beginning any SDRAM accesses. http://www.motorola.com/computer/literature 3-85...
Page 276: Ecc Codes
System Memory Controller (SMC) ECC Codes When the Hawk reports a single-bit error, software can use the syndrome that was logged by the Hawk to determine which bit was in error. Table 3-21 shows the syndrome for each possible single bit error. Table 3-22 shows the same information ordered by syndrome.
Page 277: Table 3-22. Single Bit Errors Ordered By Syndrome Code
$AC rd14 rd13 rd44 ckd4 rd53 rd50 rd46 rd49 rd43 rd39 rd63 rd40 rd16 rd17 rd60 rd62 rd59 rd56 rd12 rd11 rd10 rd61 rd58 rd57 rd20 rd28 rd36 http://www.motorola.com/computer/literature 3-87...
Page 278 System Memory Controller (SMC) 3-88 Computer Group Literature Center Web Site...
Page 279: Introduction
PCI arbitration must be provided by the host board. Hawk MPIC External Interrupts The MVME5100 Hawk MPIC is fully compliant with the industry standard Multi-Processor Interrupt Controller Specification. Following a power-up reset, the MPIC is configured to operate in the parallel interrupt delivery mode on the MVME5100 series: Table 4-1.
Page 280 Hawk Programming Details Table 4-1. MPIC Interrupt Assignments (Continued) MPIC Edge/ Polarity Interrupt Source Notes Level IRQ9 Level PCI-PMC1 INTA#, PMC2 INTB#, PCIX INTA# IRQ10 Level PCI-PMC1 INTB#, PMC2 INTC#, PCIX INTB# IRQ11 Level PCI-PMC1 INTC#, PMC2 INTD#, PCIX INTC# IRQ12 Level PCI-PMC1 INTD#, PMC2 INTA#, PCIX...
Page 281: 8259 Interrupts
Cascade Interrupt from INT2 RTCX1/ IRQ8_ INT2 Edge ABORT Switch, RTC IRQ8_ IRQ9 Level Watch Dog 1/2 PIRQA_ IRQ10 Level LAN (on front) IRQ11 Level Internal USB controller MSDT/ IRQ12 Edge High Not Used IRQ12 PIRQC_ IRQ13 LAN (to rear) http://www.motorola.com/computer/literature...
Page 282 Hawk Programming Details Table 4-2. PBC ISA Interrupt Assignments (Continued) PSIO Routed to Edge/ Interrupt Source Level Input IRQ14 IRQ14 Edge High Primary IDE interface IRQ15 IRQ15 Level PMC1 or PMC2 Interrupt IRQ3 IRQ3 INT1 Level COM2 or COM4 Interrupt IRQ4 IRQ4 Level...
Page 283: Exceptions
Exceptions Exceptions Sources of Reset There are five potential reset sources on the MVME5100 series. They are as follows: 1. Power-On Reset 2. RESET Switch 3. Watchdog Timer Reset 4. Software generated Module Reset using MODRST Bit Register. 5. Reset generated from system bus Each source of reset will result in a reset of the processor, Hawk ASIC, and all other on-board logic.
Page 284: Error Notification And Handling
The Hawk ASIC can detect certain hardware errors and can be programmed to report these errors via the MPIC interrupts or the Machine Check Interrupt. The following table summarizes how the hardware errors are handled by the MVME5100 series: Table 4-3. Error Notification and Handling Cause...
Page 285: Endian Issues
Little-Endian, it is easy to misinterpret the processing scheme. For that reason, provisions have been made to accommodate the handling of endian issues within the MVME5100. The following figures show how the MVME5100 series handles the endian issue in Big-Endian and Little-...
Page 286: Figure 4-2. Little-Endian Mode
Hawk Programming Details Little-Endian PROGRAM Little Endian Big Endian EA Modification (XOR) Hawk DRAM 60X System Bus Hawk Big-Endian EA Modification Little-Endian PCI Local Bus Figure 4-2. Little-Endian Mode Computer Group Literature Center Web Site...
Page 287: Processor/Memory Domain
(from PCI). In this case, no byte swapping is done. PCI Domain The PCI bus is inherently Little-Endian and all devices connected directly to PCI will operate in Little-Endian mode, regardless of the mode of operation in the processor’s domain. http://www.motorola.com/computer/literature...
Page 288 Hawk Programming Details 4-10 Computer Group Literature Center Web Site...
Page 289: Motorola Computer Group Documents
ARelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature...
Page 290: Manufacturers' Documents
Table A-2. Manufacturers’ Documents Publication Document Title Number MPC750 RISC Microprocessor Users Manual MPC750UM/AD Motorola Literature Distribution Center 8/97 Telephone: (800) 441-2447 or (303) 675-2140 WebSite: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com MPC7400 RISC Microprocessor Users Manual MPC7400UM/D...
Page 291 Table A-2. Manufacturers’ Documents (Continued) Publication Document Title Number Texas Instruments TL16C550C UART Data Sheet TL16550 Texas Instruments http://www.ti.com M48T37V CMOS 32Kx8 Timekeeper SRAM Data Sheet M48T37V SGS Thomson Microelectronics tap//.us.st.com 2-Wire Serial CMOS EEPROM Data Sheet AT24C04 Atmel Corporation http://www.atmel.com/atmel/support/ http://www.motorola.com/computer/literature...
Page 292: Related Specifications
Related Specifications Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice. Table A-3.
Page 293: Vital Product Data (Vpd) Introduction
Appendix A of this manual. Information that is contained in the VPD includes: Marketing Product Number (e.g., MVME5100-013x) Factory Assembly Number (e.g., 01-W3403F01) Serial number of the specific MVME5100 Processor family number (e.g., 750, 7410, etc.) Hardware clock frequencies (internal, external, fixed, PCI bus) Component configuration information (connectors, Ethernet addresses, FLASH bank ID, L2 cache ID) Security information (VPD type, version and rev.
Page 294: How To Modify The Vpd Information
MVME5100 VPD Reference Information – Displays most of the identification strings and hardware clock frequencies Serial EEPROM command - srom;i – Can be used as a byte viewer Indirect block move command - ibm<addr>;i – Reads the entire SROM block to memory Memory display command - md<addr>...
Page 295: What Happens If The Vpd Information Is Corrupted
The board may be very unstable if it reaches the prompt Device drivers, diagnostic tests, and firmware commands may hang or fail in unexpected ways How to Fix Wrong VPD Problems If you suspect that your board has problems as a result of wrong VPD information, perform the following: http://www.motorola.com/computer/literature...
Page 296: Vpd Definitions - Packet Types
MVME5100 VPD Reference Information Press the abort switch during startup (double-button reset - reset/abort) to enter the safe mode (at this point, the firmware will ignore all SROM contents and reset) Use the srom, ibm, or update command to change the VPD to the...
Page 297 A table found later in this document further describes this packet. VLSI Device Revisions/Versions Binary Host PCI-Bus Clock Frequency in Hertz (e.g., Integer (4- 33,333,333 decimal, etc.) byte) L2 Cache Configuration Binary A table found later in this document further describes this packet. http://www.motorola.com/computer/literature...
Page 298 MVME5100 VPD Reference Information Table B-1. VPD Packet Types (Continued) Size Description Data Notes Type VPD Revision. A table found later in this section Binary further describes this packet. Reserved User Defined An example of a user defined packet could be the type of LCD panel connected in an MPC821 based application.
Page 299: Table B-2. Mcg Product Configuration Options Data
Ethernet device 2 connector present PCO_ENET3_CONN Ethernet device 3 connector present PCO_ENET4_CONN Ethernet device 4 connector present PCO_SCSI1_CONN SCSI device 1 connector present PCO_SCSI2_CONN SCSI device 2 connector present PCO_SCSI3_CONN SCSI device 3 connector present PCO_SCSI4_CONN SCSI device 4 connector present http://www.motorola.com/computer/literature...
Page 300 MVME5100 VPD Reference Information Table B-2. MCG Product Configuration Options Data (Continued) Bit Number Bit Mnemonic Bit Description PCO_SERIAL1_CONN Serial device 1 connector present PCO_SERIAL2_CONN Serial device 2 connector present PCO_SERIAL3_CONN Serial device 3 connector present PCO_SERIAL4_CONN Serial device 4 connector present...
Page 301: Table B-3. Flash Memory Configuration Data
Bank Number of FLASH Memory Array: 0 = A, 1 = B FMC_SPEED ROM Access Speed in Nanoseconds FMC_SIZE Total Bank Size (Should agree with the physical organization above): 00=256K, 01=512K, 02=1M, 03=2M, 04=4M, 05=8M A product may contain multiple FLASH memory configuration packets. http://www.motorola.com/computer/literature...
Page 302: Vpd Definitions - L2 Cache Configuration Data
MVME5100 VPD Reference Information VPD Definitions - L2 Cache Configuration Data The L2 cache configuration data packet consists of byte fields that show the size, organization, and type of the L2 cache memory array. Note: The PPMCBASE does not contain L2 Cache . The following table(s) further describe the L2 cache memory configuration VPD data packet.
Page 303 01 - 1:1 (1) 02 - 3:2 (1.5) 03 - 2:1 (2) 04 - 5:2 (2.5) 05 - 3:1 (3) A product may contain multiple L2 cache configuration packets. This product, the PPMCBASE, does not contain a L2 Cache device. http://www.motorola.com/computer/literature B-11...
Page 304: Vpd Definitions - Vpd Revision Data
MVME5100 VPD Reference Information VPD Definitions - VPD Revision Data The VPD revision data packet consists of byte fields that indicate the type, version, and revision of the vital product data. The following table(s) further describe the VPD revision data packet.
Page 305 |= 1; cbyte >>= 1; crc_flipped = 0; for (index = 0; index < 32; index++) { crc_flipped <<= 1; dbit = crc & 1; crc >>= 1; crc_flipped += dbit; crc = crc_flipped ^ 0xffffffff; return (crc); http://www.motorola.com/computer/literature B-13...
Page 306: Configuration Checksum Calculation Code
MVME5100 VPD Reference Information Configuration Checksum Calculation Code /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *...
Page 307: Serial Presence Detect (Spd) Checksum Calculation
5. Store the result (single byte) in address 63 as “Checksum.” Note The same result can be obtained by adding the binary values in addresses 0-62 and eliminating all but the low order byte. The low order byte is the “Checksum.” http://www.motorola.com/computer/literature B-15...
Page 308 MVME5100 VPD Reference Information Example of a Checksum Calculation: SPD Byte Address Serial PD Convert to Decimal 00 (0x00) 0010 0100 > 01 (0x01) 1111 1110 > +254 02 (0x02) 0000 0000 > 03 (0x03) 0000 0000 > > >...
Page 309 Index Numerics Hawk’s internal 2-34 PPC 2-15, 2-16 32-Bit Counter 3-72 arbitration 3-72 from PCI Master 2-28 8259 Interrupts latency 2-29 parking 2-37 A0-A31 architectural overview AACK ARTRY_ 3-11 as used with PPC Slave access timing (ROM) 3-19, 3-20 big to little endian data swap 2-39 address big-endian mode...
Page 310 Index explained 2-26 cycle types cache 3-11 coherency restrictions 3-11 coherency SMC 3-11 support 2-25, 2-29 data Cache Control Register 1-10 discarded from prefetched reads 2-13 Cache Speed 1-10 data parity CHRP memory 2-17 CHRP Memory Maps (suggested) Data Parity Error Address Register CLK FREQUENCY 3-44 3-61...
Page 311 General Purpose Registers 2-96 Ethernet Controller 1-16 generating Ethernet Interfaces PCI configuration cycles 2-31 exceptions PCI cycles 2-29 when programming MVME5100 PCI interrupt acknowledge cycles 2-34 exclusive access 2-29 PCI memory and I/O cycles 2-30 PCI Slave 2-25 PCI special cycles 2-33...
Page 312 Index Global Configuration Register 2-114 Hawk’s PCI arbiter priority schemes 2-35 Hawk’s SMC Hardware Control-Status Register 2-77 overview Hawk HCSR address parity 3-10 Hardware Control-Status Register 2-77 as MPU/PCI bus bridge controller ASIC Header/Type Register 2-101 1-15 block diagram configuration options 3-35 I/O Base Register data parity...
Page 313 Multi-Processor Interrupt Controller Lock Resolution MVME Key Features programmable 2-46 MVME5100 endian issues sources of reset Main Memory MVME5100 Block Diagram map decoders MVME510x VME Processor Module PPC to PCI mapping PPC address NVRAM master initiated termination 2-28 NVRAM/RTC & Watchdog Timer...
Page 314 Index Master Command Codes 2-27 Hawk Master explained PPC register map 2-68 purpose of interface 2-19 Registers described 2-40 registers 2-97 retuning write thresholds 2-11 slave 2-22 spread I/O addressing 2-30 Slave disconnect scenarios 2-24 watchdog timers 2-42 slave response command types 2-23 PHB-Detected Errors Destination Register Slave with PCI Master...
Page 315 Processor Version Register (PVR) General Purpose 2-96 processor/memory domain Global Configuration 2-114 MPC750 Hardware Control-Status Register 2-77 Processors Header Type 2-101 programmable DMA Controller Interprocessor Interrupt Dispatch 2-126 Programmable Lock Resolution 2-46 Interrupt Acknowledge 2-127 programming details 1-1, http://www.motorola.com/computer/literature IN-7...
Page 316 Index IPI Vector/Priority (MPIC) 2-117 SMC SDRAM Speed Attributes 3-68 MPIC 2-110 SMC tben 3-73 MPIC I/O Base Address 2-102 SMC Vendor/Device Register 3-39 MPIC Memory Base 2-102 Spurious Vector (MPIC) 2-118 2-97 Timer Basecount (MPIC) 2-120 PCI Interrupt Acknowledge 2-87 Timer Current Count (MPIC) 2-119...
Page 317 3-56 SDRAM Enable and Size Register ROM Speed Attributes Register 3-58 3-66 Scrub/Refresh Register 3-51 SDRAM Speed Attributes Register SDRAM Base Address Register 3-43, 3-68 3-67 Serial Presence Detect (SPD) 3-76 SDRAM Enable and Size Register 3-41, 3-66 http://www.motorola.com/computer/literature IN-9...
Page 318 Hawk 3-74 PPC originated/PCI bound described Software Readable Header Register 1-28 transactions sources of reset PPC Slave limits MVME5100 unable to retry 3-76 transfer types SPD JEDEC standard definition 1-12 generated by PPC Master 2-13 Speculative PCI Request 2-47...
Page 319 1-10 VPD/SPD explained 1-14 Watchdog Timer registers 2-43 watchdog timers as part of PHB 2-42 WDTxCNTL register 2-43 WDTxCNTL Registers 2-92 WDTxSTAT Registers 2-96 write posting as part of PHB tuning 2-11 writing to the control registers 3-74 http://www.motorola.com/computer/literature IN-11...
Page 320 Index IN-12 Computer Group Literature Center Web Site...

Motorola MVME5100 Programmer's Reference Manual

About this Manual

CHAPTER 1 Product Data and Memory Maps

CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

CHAPTER 3 System Memory Controller (SMC)

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