Table 2-3. Ppc Master Write Posting Options; Table 2-4. Ppc Master Read Ahead Options - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
WXFT
RXFT RMFT
xx
2-12
threshold should be lowered to anticipate any additional latencies incurred
by the PPC Master on the PPC60x bus.
available write posting options.

Table 2-3. PPC Master Write Posting Options

WPEN PPC60x Start
xx 0 FIFO = 1 dword
00 1 FIFO >= 4 cache lines
01 1 FIFO >= 3 cache lines
10 1 FIFO >= 2 cache lines
11 1 FIFO >= 1 cache lines
The PPC Master has an optional read ahead mode controlled by the RAEN
bit in the PSATTx registers that allows the PPC Master to prefetch data in
bursts and store it in the PCI FIFO. The contents of the PCI FIFO is then
used to satisfy the data requirements for the remainder of the PCI read
transaction. The PHB read ahead mechanism is tuned for maximum
efficiency during typical operation conditions. If excessive latencies are
encountered on the PPC60x bus, it may be necessary to tune the read ahead
mechanism to compensate for this. Additional tuning of the read-ahead
function is controlled by the RXFT/RMFT (Read Any FIFO
Threshold/Read Multiple FIFO Threshold) fields in the PSATTx registers.
These fields can be used to characterize when the PPC Master continues
reading ahead with respect to the PCI FIFO threshold. The FIFO threshold
should be raised to anticipate any additional latencies incurred by the PPC
Master on the PPC60x bus.
ahead options.

Table 2-4. PPC Master Read Ahead Options

PCI
RAEN
Command
xx 0 Read
Read Line
Table 2-3
PPC60x Continuation
FIFO = 1 dword
FIFO >= 1 cache line
FIFO >= 1 cache line
FIFO >= 1 cache line
FIFO >= 1 cache line
Table 2-4 summarizes the PHB available read
Initial
Continuation
Read Size
1 cache PCI received
line data and
FRAME_
asserted
Computer Group Literature Center Web Site
summarizes the PHB
Subsequent
Read Size
1 cache line