Motorola MVME5100 Programmer's Reference Manual page 143

XBTOI
XDPEI
PPERI
PSERI
PSMAI
PRTAI
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PPC Address Bus Time-out Interrupt Enable. When this
bit is set, the XBTO bit in the MERST register will be
used to assert an interrupt through the MPIC interrupt
controller. When this bit is clear, no interrupt will be
asserted.
PPC Data Parity Error Interrupt Enable. When this bit is
set, the XDPE bit in the ESTAT register will be used to
assert an interrupt through the MPIC. When this bit is
clear, no interrupt will be asserted.
PCI Parity Error Interrupt Enable. When this bit is set, the
PPER bit in the ESTAT register will be used to assert an
interrupt through the MPIC interrupt controller. When this
bit is clear, no interrupt will be asserted.
PCI System Error Interrupt Enable. When this bit is set,
the PSER bit in the ESTAT register will be used to assert
an interrupt through the MPIC interrupt controller. When
this bit is clear, no interrupt will be asserted.
PCI Master Signalled Master Abort Interrupt Enable.
When this bit is set, the PSMA bit in the ESTAT register
will be used to assert an interrupt through the MPIC
interrupt controller. When this bit is clear, no interrupt will
be asserted.
PCI Master Received Target Abort Interrupt Enable.
When this bit is set, the PRTA bit in the ESTAT register
will be used to assert an interrupt through the MPIC
interrupt controller. When this bit is clear, no interrupt will
be asserted.
Registers
2
2-81