Motorola MVME5100 Programmer's Reference Manual page 309

Numerics
32-Bit Counter 3-72
SMC 3-72
8259 Interrupts 4-3
A
A0-A31 3-4
AACK
as used with PPC Slave
access timing (ROM) 3-19,
address
Address Parity Error Address Register
3-71
Address Parity Error Log Register
SMC
3-70
data stepping 2-29
decoders PCI to PPC
decoders PPC to PCI
limits on PHB map decoding
mapping PPC 2-6
modification for little endian transfers
2-40
offsets, as part of map decoders
parity PPC60x 3-10
pipelining 3-6
transfers 3-9
addressing
mode for PCI Master
to PCI Slave 2-23
addressing mode
PCI Slave limits
arbiter
as controlled by the XARB register
2-7
3-20
2-6
2-7
2-6
2-21
2-28
2-24
2-16
Hawk's internal
PPC 2-15, 2-16
arbitration
from PCI Master
latency 2-29
parking 2-37
architectural overview
ARTRY_ 3-11
B
big to little endian data swap
big-endian mode 4-7
bit descriptions 3-38
bit ordering convention
SMC 3-1
block diagram 1-3, 2-3
Hawk SMC 3-3
Hawk used with SDRAM
block diagrams
Hawk with SDRAMs
Board Last Reset Register
bridge
PHB 2-1
PowerPC to PCI Local Bus Bridge
burst write bandwidth
Bus Clock Frequency
bus cycle types
on the PCI bus 2-29
Bus Hog
PPC master device
bus interface (60x)
to SMC 3-9
Index
2-34
2-28
2-4
2-39
3-2
3-2
1-31
2-1
1-1
1-1
2-14
IN-1