Ppc Bus Interface - Motorola MVME5100 Programmer's Reference Manual

All PCI originated PPC bound transactions utilize the PCI Slave and PPC
Master functions for maintaining bus tracking and control. During both
write and read transactions, the PCI Slave places command information
into the PCI FIFO. The PPC Master draws this command information from
the PCI FIFO when it is ready to process the transaction. During write
transactions, write data is captured from the PCI bus within the PCI Input
block. This data is fed into the PCI FIFO. The PPC Output block removes
the data from the FIFO and presents it to the PPC60x bus. During read
transactions, read data is captured from the PPC60x bus within the PPC
Input block. From there, the data is fed into the PCI FIFO. The PCI Output
block removes the data from the FIFO and presents it to the PCI bus.
The MPIC is hosted by the PHB. A custom MPIC Interface is provided to
allow write data and control to be passed to the MPIC and to allow read
data to be passed back to the PHB. The MPIC Interface is controlled
exclusively by the PCI Slave.
The data path function imposes some restrictions on access to the MPIC,
the PCI Registers, and the PPC Registers. The MPIC and the PCI Registers
are only accessible to PCI originated transactions. The PPC Registers are
only accessible to PPC originated transactions.
The PHB has several small blocks that support various PPC functions.
Arbitration is provide by the PPC Arbiter block. Cache line locking (via
PCI Lock) is handled by the PPC Lock block. Finally, a timer function is
implemented in the PPC Timer block.
The PHB also provides miscellaneous support for various PCI functions.
Arbitration on the PCI bus is handled by the PCI Arbiter block. Parity
checking and generation is handled within the PCI Parity block.

PPC Bus Interface

The PPC Bus Interface connects directly to one MPC750 or MPC7400
microprocessor and one peripheral PPC60x master device. It uses a subset
of the capabilities of the PPC bus protocol.
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Functional Description
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