Hawk I2C Interface And Configuration Information - Motorola MVME5100 Programmer's Reference Manual

The Hawk ASIC also provides an Multi-Processor Interrupt Controller
(MPIC) to handle various interrupt sources. The interrupt sources are: Four
MPIC Timer Interrupts, the interrupts from all PCI devices, and the two
software interrupts.
2
Hawk I C interface and configuration information
The Hawk ASIC has an I
interface bus: Serial Clock Line (SCL) and Serial Data Line (SDA)
composed of two 256 x 8 Serial EEPROM's.
This interface has master-only capability and is used to communicate the
configuration information to a slave I
EEPROM is used to maintain the configuration information related to the
board (Vital Product Data; VPD, User Configuration Data; UCD) and a
separate EEPROM for on-board Memory Subsystem Data (MSD).
If an optional memory mezzanine is used, that mezzanine shall contain a
separate EEPROM with its own memory subsystem data. Each slave
device connected to the I
address.
There can be seven slave devices connected to the I
MVME5100. The VPD address is $A0. The UPD address is $A2.
The on-board MSD address (Memory Bank A and B) is $A8. The optional
Memory Mezzanine 1 MSD addresses is $AA (Memory Bank C) and $AC
(Memory Bank E) for mezzanine 2.
The IPMC761 VPD address is $A4. A digital thermometer (DS1621) I
address is $A6. Some configuration options in the Hawk ASIC must be
configured at power-up reset time before software performs any accesses
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2
C (Inter-Integrated Circuit) two-wire serial
2
C serial EEPROM. A separate
2
C bus is software addressable by a unique
Hawk ASIC
2
C bus on the
2
C
1-13
1