Hardware Control-Status/Prescaler Adjust Register - Motorola MVME5100 Programmer's Reference Manual

Hardware Control-Status/Prescaler Adjust Register

The Hardware Control-Status Register (HCSR) provides hardware
specific control and status information for the PHB. The bits within the
HCSR are defined as follows:
Address
Bit
Name
Operation
Reset
XPRx
SPRQ
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$FEFF0010
HCSR
PPC/PCI Clock Ratio. This is a read only field that is used
to indicate the clock ratio that has been established by the
PHB at the release of reset. The encoding of this field is
shown in the following table.
XPR PPC60x/PCI clock ratio
000 Undefined
001 1:1
010 2:1
011 3:1
100 3:2
101 Undefined
110 5:2
111 Undefined
Speculative PCI Request. If set, the PHB PCI Master will
perform speculative PCI requesting when a PCI bound
transaction has been retried due to bridge lock resolution.
If cleared, the PCI Master will only request the PCI bus
when a transaction is pending within the PHB FIFOs.
XPAD
R R/W
$00 $9C
Registers
2
2-77