Table 3-16. Trc Encoding; Table 3-17. Tras Encoding - Motorola MVME5100 Programmer's Reference Manual

cl3
trc0,1,2
tras0,1
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When cl3 is cleared, the SMC assumes that the SDRAM runs
with a CAS_ latency of 2. When cl3 is set, the SMC assumes that
it runs with a CAS_ latency of 3. Note that writing so as to
change cl3 from 1 to 0 or vice-versa causes the SMC to perform
a mode-register-set operation to the SDRAM array. The mode-
register-set operation updates the SDRAM's CAS latency to
match cl3.
Together trc0,1,2 determine the minimum number of clock
cycles that the SMC assumes the SDRAM requires to satisfy its
Trc parameter. These bits are encoded as follows:

Table 3-16. Trc Encoding

trc0,1,2 Minimum Clocks for Trc
%000
%001
%010
%011
%100
%101
%110
%111
Together tras0,1 determine the minimum number of clock
cycles that the SMC assumes the SDRAM requires to satisfy its
tRAS parameter. These bits are encoded as follows:

Table 3-17. tras Encoding

tras0,1 Minimum Clocks for tras
%00
%01
%10
%11
Programming Model
8
9
10
11
reserved
reserved
6
7
4
5
6
7
3
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