Motorola MVME5100 Programmer's Reference Manual page 310

C
cache
coherency restrictions
coherency SMC
support 2-25,
Cache Control Register
Cache Speed
CHRP memory
CHRP Memory Maps (suggested)
CLK FREQUENCY
CLK Frequency Register
SMC 3-44
clock frequency
combining, merging, and collapsing
command types
from PCI Master
PPC slave
CONADD and CONDAT Registers
CONFIG_ADDRESS Register
CONFIG_DATA Register
configuration
options on Hawk
registers
requirements on Hawk
type, as used by PHB
configurations
MVME21xx
contention
between PCI and PPC
handling explained (PHB)
control bit
descriptions
core frequency
Critical Word First (CWF)
as supported by PCI Master
I
CSR
N
accesses to SMC
D
architecture of SMC
E base address
reads and writes
X
Current Task Priority Register
CWF burst transfers
IN-2
3-11
3-11
2-29
1-10
1-10
1-4
1-6
3-44
3-44
2-28
2-23
2-27
2-8
1-19
2-106
2-109
3-35
2-19
3-35
2-31
xxii
2-45
2-45
3-38
1-9
2-26
3-34
3-35
3-35
3-35
2-127
explained 2-26
cycle types
SMC 3-11
D
data
discarded from prefetched reads
data parity
PPC 2-17
Data Parity Error Address Register
SMC 3-61
Data Parity Error Log Register
SMC 3-60
Data Parity Error Lower Data Register
SMC 3-62
Data Parity Error Upper Data Register
SMC 3-61
data throughput
PPC Slave to PCI Master
data transfer
PPC Master rates 2-10
relationship between PCI Slave and
PPC60x bus
data transfers
SMC 3-9
decoder
priorities 2-21
decoders
address PCI to PPC
for PCI to PPC addressing
PPC to PCI 2-7
delayed transactions
PCI Slave 2-24
derc 3-47
device selection 2-24
Disable Error Correction control bit
documentation, related B-1
DRAM
connection diagram
enable bits 3-41
size control bits 3-41
Computer Group Literature Center Web Site
Index
2-13
2-9
2-11
2-6
2-20
3-47
3-4