Ppc Error Status Register - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

PPC Error Status Register

2
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
2-82
The Error Status Register (ESTAT) provides an array of status bits
pertaining to the various errors that the PHB can detect. The bits within the
ESTAT are defined in the following paragraphs.
1
0
R
$00
OVF Error Status Overflow. This bit is set when any error is
detected and any of the error status bits are already set. It
may be cleared by writing a 1 to it; writing a 0 to it has no
effect.
XBTO PPC Address Bus Time-out. This bit is set when the PPC
timer times out. It may be cleared by writing a 1 to it;
writing a 0 to it has no effect. When the XBTOM bit in the
EENAB register is set, the assertion of this bit will assert
MCHK to the master designated by the XID field in the
EATTR register. When the XBTOI bit in the EENAB
register is set, the assertion of this bit will assert an
interrupt through the MPIC.
XDPE PPC Data Parity Error. This bit is set when the PHB
detects a data bus parity error. It may be cleared by writing
a 1 to it; writing a 0 to it has no effect. When the XDPEM
bit in the EENAB register is set, the assertion of this bit
will assert MCHK to the master designated by the XID
field in the EATTR register. When the XDPEI bit in the
EENAB register is set, the assertion of this bit will assert
an interrupt through the MPIC.
$FEFF0024
1 1 1 1 1 1 1 1 1
1 2 3 4 5 6 7 8 9
R R
$00 $00
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2 2 2 2 2 2 2 2 2
0 1 2 3 4 5 6 7 8
ESTAT
2 3 3
9 0 1