Ppc Error Test/Error Enable Register - Motorola MVME5100 Programmer's Reference Manual

PPC Error Test/Error Enable Register

The Error Test Register (ETEST) provides you with a way to send certain
types of errors to test the PHB error capture and status circuitry. The bits
within the ETEST are defined as follows:
Address
Bit
Name
Operation
Reset
DPEx
APEx
The Error Enable Register (EENAB) controls how the PHB is to respond
to the detection of various errors. In particular, each error type can
uniquely be programmed to generate a machine check, generate an
interrupt, generate both, or generate neither. The bits within the ETEST are
defined as follows:
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$FEFF0020
ETEST
Data Parity Error Enable. These bits are used for test
reasons to purposely inject data parity errors whenever the
PHB is sourcing PPC data. A data parity error will be
created on the corresponding PPC data parity bus if a bit
is set. For example, setting DPE0 will cause DP0 to be
generated incorrectly. If the bit is cleared, the PHB will
generate correct data parity.
Address Parity Error Enable. These bits are used for test
reasons to purposely inject address parity errors whenever
the PHB is acting as a PPC bus master. An address parity
error will be created on the corresponding PPC address
parity bus if a bit is set. For example, setting APE0 will
cause AP0 to be generated incorrectly. If the bit is cleared,
the PHB will generate correct address parity.
Registers
EENAB
2-79
2