Dual Tl16C550 Uarts; Table 1-10. 16550 Access Registers - Motorola MVME5100 Programmer's Reference Manual

Dual TL16C550 UARTs

The MVME5100 implementation of the Dual TL16C550 UARTs are fully
compliant with the PowerPlus II Programming Model for UART
Registers. The following tables reflect this model.
The MVME5100 uses UART-1 and UART-2 for asynchronous serial
debug ports (four are allowed by the PowerPlus II Programming Model).
The first UART (UART-1) is addressed at External Register Set Address
Offset $8000 (FEF8 8000). The second (UART-2) is addressed at offset
$8200 (FEF8 8200). The UART 8-bit data port (RD0-RD7) is connected
to the most significant bits of the 64-bit External Register Set. The UART
port addressing occurs on 16-byte address boundaries, and are backward
compatible with the PPMC750.
Required or External Register
Optional Set Address Offset
UART-1 Registers
UART-2 Registers
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Table 1-10. 16550 Access Registers

8000 Receiver Buffer (Read), Transmitter Holding (Write)
8010 Interrupt Enable
8020 Interrupt Identification (Read), FIFO Control (Write)
8030 Line Control
8040 MODEM Control
8050 Line Status
8060 MODEM Status
8070 Scratch
8200 Receiver Buffer (Read), Transmitter Holding (Write)
8210 Interrupt Enable
8220 Interrupt Identification (Read), FIFI Control (Write)
8230 Line Control
8240 MODEM Control
8250 Line Status
8260 MODEM Status
8270 Scratch
PCI Local Bus
Function
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