Table 3-6. Ppc60X Bus To Rom/Flash Access Timing (80Ns @ 100 Mhz); Table 3-7. Ppc60X Bus To Rom/Flash Access Timing (50Ns @ 100 Mhz) - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)
3
ACCESS TYPE
4-Beat Read
4-Beat Write
1-Beat Read (1 byte)
1-Beat Read (2 to 8
bytes)
1-Beat Write
ACCESS TYPE
4-Beat Read
4-Beat Write
1-Beat Read (1 byte)
1-Beat Read (2 to 8
bytes)
1-Beat Write
3-20
Table 3-6. PPC60x Bus to ROM/Flash Access Timing
(80ns @ 100 MHz)
CLOCK PERIODS REQUIRED FOR:
1st Beat
16 64
Bits Bits
54 18
18 18
54 18
21 21
Notes The information in
configured for devices with an access time equal to 8 clock
periods.
Table 3-7. PPC60x Bus to ROM/Flash Access Timing
(50ns @ 100 MHz)
CLOCK PERIODS REQUIRED FOR:
1st Beat
16 64
Bits Bits
42 15
N/A
15 15
42 15
21 21
2nd Beat 3rd Beat
16 64 16 64
Bits Bits Bits Bits
48 12 48 12
N/A
- - - -
- - - -
- - - -
Table 3-6 applies to access timing when
2nd Beat 3rd Beat
16 64 16 64
Bits Bits Bits Bits
36 9 36 9
- - - -
- - - -
- - - -
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Total
Clocks
4th Beat
16 64 16 64
Bits Bits Bits Bits
48 12 198 54
N/A
- - 18 18
- - 54 18
- - 21 21
Total
Clocks
4th Beat
16 64 16 64
Bits Bits Bits Bits
36 9 150 42
N/A
- - 15 15
- - 42 15
- - 21 21