Error Reporting; Table 3-2. Error Reporting - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)

Error Reporting

3
Error Type
Single-Bit
Error
Double-Bit
Error
Triple- (or
greater)
Bit Error
3-12
The SMC checks data from the SDRAM during single- and four-beat reads,
during single-beat writes, and during scrubs.
takes for different errors during these accesses 60x.
Note that the SMC does not assert TEA_ on double-bit errors. In fact, the
SMC does not have a TEA_ signal pin and it assumes that the system does
not implement TEA_. The SMC can, however, assert machine check
(MCHK0_) on double-bit error.

Table 3-2. Error Reporting

Single-Beat/Four-
Single-Beat Write
Beat Read
Terminate the Terminate the
PPC60x bus cycle nor- PPC60x bus cycle nor-
mally. mally.
Provide corrected data to Correct the data read
the PPC60x bus master. from SDRAM, merge
with the write data, and
write the corrected,
merged data to SDRAM.
Assert Hawk's internal
error interrupt, if so Assert Hawk's internal
2
enabled. error interrupt, if so
enabled.
Terminate the Terminate the
PPC60x bus cycle nor- PPC60x bus cycle nor-
mally. mally.
Provide miss-corrected, Do not perform the write
raw SDRAM data to the portion of the read-mod-
PPC60x60x bus master. ify-write cycle to
SDRAM.
Assert Hawk's internal
error interrupt, if so Assert Hawk's internal
2
enabled. error interrupt, if so
Assert MCHK0_ if so enabled.
enabled. Assert MCHK0_ if so
enabled.
Some of these errors are detected correctly and are treated the same as double-bit errors. The rest could
show up as "no error" or "single-bit error", both of which are incorrect.
Table 3-2
Four-Beat Write
N/A
2
N/A
2
Computer Group Literature Center Web Site
shows the actions it
Scrub
This cycle is not seen on
the PPC60x bus.
Write corrected data
back to SDRAM if so
enabled.
1
Assert Hawk's internal
error interrupt, if so
2
enabled.
This cycle is not seen on
the PPC60x bus.
Do not perform the
write portion of the
1
read-modify-write cycle
to SDRAM.
Assert Hawk's internal
error interrupt if so
2
enabled.