Motorola MVME5100 Programmer's Reference Manual page 254

System Memory Controller (SMC)
i2_stop
3
i2_ackout
i2_enbl
2
I C Status Register
Address
Bit
Name
Operation
Reset
i2_datin
i2_err
3-64
When set, the I
2
on the I
2
the I C Transmitter Data Register and clears the i2_cmplt bit
2
in the I C Status Register. After the stop sequence has been
transmitted, the I
the i2_stop bit and then set the i2_cmplt bit in the I
Register.
When set, the I
2
on the I C bus during read cycles. This bit should be used only
2
in the I C sequential read operation and must remain cleared
for all other I
this bit should be set for every single byte received except on
the last byte in which case it should be cleared.
When set, the I
operations. If clear, reads and writes to all I
allowed but no I
READ ZERO READ ZERO
X
This bit is set whenever the I
successfully received a byte of read data from an I
device. This bit is cleared after the I
read.
This bit is set when both i2_start and i2_stop bits in the I
Control Register are set at the same time. The I
controller will then clear the contents of the I
2
C master controller generates a stop sequence
C bus on the next dummy write (data=don't care) to
2
C master controller will automatically clear
2
C master controller generates an acknowledge
2
C operations. For I
2
C master interface will be enabled for I
2
C bus operations will be performed.
$FEF800A0
READ ZERO
X
2
C master controller has
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2
C Status
2
C sequential read operation,
2
C registers are still
X
2
C bus slave
2
C Receiver Data Register is
2
C master
2
C Control
2
C
2
C