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ware is programmed into the lower sectors of Flash (0xFFE0_0000 to 0xFFE3_FFFF for
2Mbytes of FLASH or 0xFFC0_0000 to 0xFFC3_FFFF for 4 Mbytes of FLASH).
When U11 is fitted on the EVB, jumper 5 (JP5) provides an alternative hardware mecha-
nism for write protection. This feature is not available when U10 is populated.
1.2.2
SDRAM
The EVB is populated with 16 Mbytes of SDRAM. This is done with two devices (Micron
MT48LC4M16A2TG) each with a 16 bit data bus. Each device is organized as 1 Meg x 16
x 4 banks with a 16 bit data bus. One device stores the upper 16-bit word and the other the
lower 16 bit word of the MCF5271 32 bit data bus.
1.2.3
ASRAM
The EVB has a footprint for two 512K x 16 Asynchronous SRAM devices (Cypress
Semiconductor - CY7C1041CV3310ZC
populated by the user for benchmarking purposes.
Also see Section 1.2.5, "M5271EVB Memory Map".
1.2.4
Internal SRAM
The MCF5271 processor has 64-KBytes of internal SRAM memory which may be used as
data or instruction memory. This memory is mapped to 0x2000_0000 and configured as
data space but is not used by the dBUG monitor except during system initialization. After
system initialization is complete, the internal memory is available to the user. The memory
is relocatable to any 32-KByte boundary within the processor's four gigabyte address
space.
1.2.5
M5271EVB Memory Map
Interface signals to support the interface to external memory and peripheral devices are
generated by the memory controller. The MCF5271 supports 8 external chip selects,
CS[1:0] are used with external memories, and CS[7:2] are easily accessible to users via the
daughter card expansion connectors. CS[0] also functions as the global (boot) chip-select
for booting out of external flash.
Since the MCF5271 chip selects are fully programmable, the memory banks may be located
at any 64-KByte boundary within the processor's four gigabyte address space.
The default memory map for this board as configured by the Debug Monitor located in the
external FLASH bank can be found in table 1-2. The internal memory space of the
MCF5271 is detailed further in the MCF5271 Users Manual. Chip Selects 0 and 1 can be
. These memory devices (U1 and U2) may be
)
Chapter 1. M5271EVB Introduction
System Memory
1-7
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