Timer Basecount Registers - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

Timer Basecount Registers

2
Offset
Bit 3
1
Name
Operation
Reset
2-120
3 2 2 2 2 2 2 2 2
0 9 8 7 6 5 4 3 2
CI COUNT INHIBIT. Setting this bit to one inhibits counting
for this timer. Setting this bit to zero allows counting to
proceed.
BC BASE COUNT. This field contains the 31 bit count for
this timer. When a value is written into this register and the
CI bit transitions from a 1 to a 0, it is copied into the
corresponding Current Count register and the toggle bit in
the Current Count register is cleared. When the timer
counts down to zero, the Current Count register is
reloaded from the Base Count register and the timer's
interrupt becomes pending in MPIC processing.
Timer 0 - $01110
Timer 1 - $01150
Timer 2 - $01190
Timer 3 - $011D0
2 2 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3
TIMER BASECOUNT
BC
R/W
$00000000
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1 1 1
2 1 0 9 8 7 6 5 4 3 2 1 0