Ppc Arbiter/Pci Arbiter Control Registers - Motorola MVME5100 Programmer's Reference Manual

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PPC Arbiter/PCI Arbiter Control Registers

The PPC Arbiter Register (XARB) provides control and status for the PPC
Arbiter. Refer to the section titled
bits within the XARB register are defined as follows:
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
RW
Reset
0
FBRx
FSRx
FBWx
FSWx
FBR/FSR/FBW/FSW
http://www.motorola.com/computer/literature
$FEFF000C
1
1
1
1
1
1
0
1
2
3
4
5
XARB
Flatten Burst Read. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
burst read cycles. The encoding of this field is shown in
the table below.
Flatten Single Read. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
single beat read cycles. The encoding of this field is
shown in the table below.
Flatten Burst Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all burst write cycles. The encoding of this field is shown
in the table below.
Flatten Single Write. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
single beat write cycles. The encoding of this field is
shown in the table below.
Effects on Bus Pipelining
00
None
01
None
10
Flatten always
11
Flatten if switching masters
PPC Arbiter
for more information. The
1
1
1
1
2
2
2
2
2
6
7
8
9
0
1
2
3
4
PARB
Registers
2
2
2
2
2
3
3
5
6
7
8
9
0
1
2-73
2

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