Rom/Flash Interface - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)

ROM/Flash Interface

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The SMC provides the interface for two blocks of ROM/Flash. Each block
provides addressing and control for up to 64MB. Note that no ECC error
checking is provided for the ROM/Flash.
The ROM/Flash interface allows each block to be individually configured
by jumpers and/or by software as follows:
1. Access for each block is controlled by three software programmable
control register bits: an overall enable, a write enable, and a reset
vector enable. The overall enable controls normal read accesses.
The write enable is used to program Flash devices. The reset vector
enable controls whether the block is also enabled at $FFF00000 -
$FFFFFFFF. The overall enable and write enable bits are always
cleared at reset. The reset vector enable bit is cleared or set at reset
depending on external jumper configuration. This allows the board
designer to use external jumpers to enable/disable Block A/B
ROM/Flash as the source of reset vectors.
2. The base address for each block is software programmable. At reset,
Block A's base address is $FF000000, if Bank A is less than or
equal to 8MB; otherwise, it is 0xF4000000. Block B's base address
is $FF800000.
As noted above, in addition to appearing at the programmed base
address, the first 1MB of Block A/B also appears at $FFF00000-
$FFFFFFFF if the reset vector enable bit is set.
3. The assumed size for each block is software programmable. It is
initialized to its smallest setting at reset.
4. The access time for each block is software programmable.
5. The assumed width for Block A/B is determined by an external
jumper at reset time. It also is available as a status bit and cannot be
changed by software.
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