Processor Bus Memory Map; Default Processor Memory Map; Table 4-1. Processor Default View Of The Memory Map - Motorola MVME2301 Installation And Use Manual

Programming the MVME230x

Processor Bus Memory Map

4

Default Processor Memory Map

4-2
The processor memory map configuration is under the control of
the Raven bridge controller ASIC and the Falcon memory controller
chip set. The Raven and Falcon devices adjust system mapping to
suit a given application via programmable map decoder registers.
At system power-up or reset, a default processor memory map
takes over.
The default processor memory map that is valid at power-up or
reset remains in effect until reprogrammed for specific
applications. Table 4-1 defines the entire default map ($00000000 to
$FFFFFFFF).

Table 4-1. Processor Default View of the Memory Map

Processor Address
Start End
00000000 7FFFFFFF
80000000 8001FFFF
80020000 FEF7FFFF
FEF80000 FEF8FFFF
FEF90000 FEFEFFFF
FEFF0000 FEFFFFFF
FF000000 FFEFFFFF
FFF00000 FFFFFFFF
The first 1MB of Flash bank A (soldered 2MB or 4MB
Notes
Flash) appears in this range after a reset if the rom_b_rv
control bit in the FalconÕs ROM B Base/Size register is
cleared. If the rom_b_rv control bit is set, this address
range maps to Flash bank B (socketed 1MB Flash).
Size
2GB Not Mapped
128KB PCI/ISA I/O Space
2GB-16MB-640KB Not Mapped
64KB Falcon Registers
384KB Not Mapped
64KB Raven Registers
15MB Not Mapped
1MB Flash Bank A or Bank B (See Note)
DeÞnition