Mpic I/O Base Address Register; Mpic Memory Base Address Register - Motorola MVME5100 Programmer's Reference Manual
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Also See for MVME5100:
- Programmer's reference manual (270 pages) ,
- Manual (127 pages) ,
- Installation & use manual (107 pages)
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MPIC I/O Base Address Register
2
Offset
Bit
3
1
Name
Operation
Reset
MPIC Memory Base Address Register
Offset
Bit
3
1
Name
Operation
Reset
2-102
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
BASE
R/W
$0000
The MPIC I/O Base Address Register (MIBAR) controls the mapping of
the MPIC control registers in PCI I/O space.
IO/MEM IO Space Indicator. This bit is hard-wired to a logic one to
indicate PCI I/O space.
RES
Reserved. This bit is hard-wired to zero.
BASE
Base Address. These bits define the I/O space base
address of the MPIC control registers. The MIBAR
decoder is disabled when the BASE value is zero.
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
BASE
R/W
$0000
$10
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
MIBAR
$14
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
MMBAR
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1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$0000
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$0000
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