Motorola MVME5100 Programmer's Reference Manual page 18

Table 2-18. PCI I/O Register ................................................................................... 2-98
Table 2-19. MPIC Register Map............................................................................ 2-110
Table 2-20. Cascade Mode Encoding .................................................................... 2-115
Table 2-21. Tie Mode Encoding ............................................................................ 2-115
Table 3-1. 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100
SDRAMs (CAS_latency of 2) ................................................................................... 3-7
Table 3-2. Error Reporting....................................................................................... 3-12
Table 3-3. PPC60x to ROM/Flash (16 Bit Width)
Address Mapping..................................................................................................... 3-16
Table 3-4. PPC60x to ROM/Flash (64 Bit Width)
Address Mapping..................................................................................................... 3-17
Table 3-5. PPC60x Bus to ROM/Flash Access Timing
(120ns @ 100 MHz) ................................................................................................ 3-19
Table 3-6. PPC60x Bus to ROM/Flash Access Timing
(80ns @ 100 MHz) .................................................................................................. 3-20
Table 3-7. PPC60x Bus to ROM/Flash Access Timing
(50ns @ 100 MHz) .................................................................................................. 3-20
Table 3-8. PPC60x Bus to ROM/Flash Access Timing
(30ns @ 100 MHz) .................................................................................................. 3-21
Table 3-9. Register Summary .................................................................................. 3-36
Table 3-10. Block_A/B/C/D/E/F/G/H Configurations ............................................ 3-42
Table 3-11. ROM Block A Size Encoding .............................................................. 3-54
Table 3-12. rom_a_rv and rom_b_rv encoding ....................................................... 3-54
Table 3-13. Read/Write to ROM/Flash.................................................................... 3-55
Table 3-14. ROM Block B Size Encoding .............................................................. 3-57
Table 3-15. ROM Speed Bit Encodings .................................................................. 3-59
Table 3-16. Trc Encoding ........................................................................................ 3-69
Table 3-17. tras Encoding ........................................................................................ 3-69
Table 3-18. Deriving tras, trp, trcd and trc Control Bit Values
from SPD Information ............................................................................................. 3-78
Table 3-19. Programming SDRAM SIZ Bits .......................................................... 3-81
Table 3-20. Address Lists for Different Block Size Checks.................................... 3-85
Table 3-21. Syndrome Codes Ordered by Bit in Error ............................................ 3-86
Table 3-22. Single Bit Errors Ordered by Syndrome Code ..................................... 3-87
Table 4-1. MPIC Interrupt Assignments.................................................................... 4-1
Table 4-2. PBC ISA Interrupt Assignments .............................................................. 4-3
Table 4-3. Error Notification and Handling............................................................... 4-6
Table A-1. Motorola Computer Group Documents ................................................. A-1
Table A-2. Manufacturers' Documents ................................................................... A-2
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