Table 1-3. Chrp Memory Map Example - Motorola MTX Series Programmer's Reference Manual

Board Description and Memory Maps
1
Table 1-2. Default Processor Memory Map (Continued)
Processor Address
Start
FEF9 0000
FEFF 0000
FF00 0000
FFF0 0000
Processor Address
Start
0000 0000
4000 0000
FD00 0000
FE00 0000
1-6
Size
End
FEFE FFFF 384K
FEFF FFFF 64K
FFEF FFFF 15M
FFFF FFFF 1M
Notes
1. This default map for PCI/ISA I/O space allows software to
determine if the system is MPC105-based or Falcon/Raven-based
by examining either the PHB Device ID or the CPU Type Register.
2. The first 1MB of ROM/FLASH Bank A appears at this range after
a reset if the rom_b_rv control bit is cleared. If the rom_b_rv
control bit is set then this address range maps to ROM/FLASH Bank
B.
Processor CHRP Memory Map
The following table shows a recommended CHRP memory map from the
point of view of the processor.

Table 1-3. CHRP Memory Map Example

Size
End
top_dram dram_size System Memory (onboard DRAM)
FCFF FFFF 3G - 48M
FDFF FFFF 16M
FE7F FFFF 8M
Definition
Not mapped
Raven Registers
Not mapped
ROM/FLASH Bank A or Bank B
Definition
PCI Memory Space:
4000 0000 to FCFF FFFF
Zero-Based PCI/ISA Memory Space
(mapped to 00000000 to 00FFFFFF)
Zero-Based PCI/ISA I/O Space
(mapped to 00000000 to 007FFFFF)
Computer Group Literature Center Web Site
2
1, 2
3,4
3
3,5