Memory Maps; Default Processor Memory Map; Table 1-2. Mvme712-101 Rtm Features Summary; Table 1-3. Default Processor Address Map - Motorola MVME3100 Programmer's Manual

Table 1-2. MVME712-101 RTM Features Summary

Feature
I/O
Miscellaneous

Memory Maps

Default Processor Memory Map

The MPC8540 presents a default processor memory map following RESET negation. The following
table shows the default memory map from the point of view of the processor. The e500 core only
provides one default TLB entry to access boot code and it allows for accesses within the highest 4KB
of memory. To access the full 8MB of default boot space (and the 1MB of CCSR space), additional TLB
entries must be set up within the e500 core for mapping these regions. Refer to the MPC8540 Reference
Manual listed in

Table 1-3. Default Processor Address Map

Processor Address
Start
0000 0000
FF70 0000
FF80 0000
Notes
1. This is the default location for the CCSRs, but it is not mapped after reset.
2. Only FFFF F000 to FFFF FFFF is mapped after reset. The e500 core fetches the first instruction
from FFFF FFFC following a reset.
Description
– One five-row P2 backplane connector for serial and Ethernet I/O
passed from the MVME3100
– Four RJ-45 connectors for rear-panel I/O: four asynchronous
serial channels
– Two RJ-45 connectors with integrated LEDs for rear panel I/O:
one 10/100/1000 Ethernet channel and one 10/100 Ethernet
channel
– One PIM site with rear-panel I/O
– Four rear-panel status indicators: 10/100/1000 and 10/100
Ethernet link/speed and activity LEDs
Appendix A, Related Documentation, for details.
End Size
FF6F FFFF 4087M
FF7F FFFF 1M
FFFF FFFF 8M
Chapter 1 Board Description and Memory Maps
Definition
Not mapped
MPC8540 CCS Registers
Flash
MVME3100 Programmer's Guide (V3100A/PG1)
Notes
1
2
5