Pci Registers; Table 2-17. Pci Configuration Register - Motorola MVME5100 Programmer's Reference Manual

PCI Registers

The PCI Configuration Registers are compliant with the configuration
register set described in the PCI Local Bus Specification, Revision 2.1.
The CONFIG_ADDRESS and CONFIG_DATA registers described in
this section are accessed from the PPC bus within PCI I/O space.
All write operations to reserved registers will be treated as no-ops. That is,
the access will be completed normally on the bus and the data will be
discarded. Read accesses to reserved or unimplemented registers will be
completed normally and a data value of 0 will be returned.
The PCI Configuration Register map of the PHB is shown in
The PCI I/O Register map of the PHB is shown in

Table 2-17. PCI Configuration Register

3 3 2 2 2 2 2 2 2
1 0 9 8 7 6 5 4 3
DEVID
STATUS
PSOFF0
PSOFF1
PSOFF2
PSOFF3
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2 2 2 1 1 1 1 1 1
2 1 0 9 8 7 6 5 4
CLASS
HEADER
MIBAR
MMBAR
PSADD0
PSADD1
PSADD2
PSADD3
1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1 0
VENID
COMMAND
REVID
PSATT0
PSATT1
PSATT2
PSATT3
Registers
Table 2-17.
Table 2-18
<--- Bit
$00
$04
$08
$0C
$10
$14
$18 - $7C
$80
$84
$88
$8C
$90
$94
$98
$9C
2-97
2