Motorola MVME5100 Programmer's Reference Manual page 222

System Memory Controller (SMC)
3
3-32
As long as the slave device receives an acknowledge, it will continue to
increment the word address and serially clock out sequential data words.
2
The I C sequential read operation is terminated when the I
controller does not respond with an acknowledge. This can be
accomplished by setting only the i2_enbl bit in the I
before receiving the last data word. A stop sequence then must be
transmitted to the slave device by first setting the i2_stop and i2_enbl bits
2
in the I C Control Register and then writing a dummy data (data=don't
2
care) to the I C Transmitter Data Register. The I
now be polled to test i2_cmplt bit for the operation-complete status. The
stop sequence will relinquish the ASIC master's possession of the I
Figure 3-9 shows the suggested software flow diagram for programming
2
the I C sequential read operation.
2
C Control Register
2
C Status Register must
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2
C master
2
C bus.