Motorola MVME5100 Programmer's Reference Manual page 90

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
Entity Addressed
PPC Mapped PCI Space
2-28
Table 2-8. PCI Master Command Codes (Continued)
PPC
Transfer Type
-- Unsupported --
Read
-- Unsupported --
Addressing
The PCI Master generates all memory transactions using the Linear
Incrementing addressing mode.
Combining, Merging, and Collapsing
The PCI Master does not participate in any of these protocols.
Master Initiated Termination
The PCI Master can handle any defined method of target retry, target
disconnect, or target abort. If the target responds with a retry, the PCI
Master waits for the required two clock periods and attempts the
transaction again. This process continues indefinitely until the transaction
is completed, the transaction is aborted by the target, or if the transaction
is aborted due to a PHB detected bridge lock. The same happens if the
target responds with a disconnect and there is still data to be transferred.
If the PCI Master detects a target abort during a read, any untransferred
read data is filled with ones. If the PCI Master detects a target abort during
a write, any untransferred portions of data will be dropped. The same rule
applies if the PCI Master generates a Master Abort cycle.
Arbitration
The PCI Master can support parking on the PCI bus. There are two cases
where the PCI Master continuously asserts its request.
If the PCI Master starts a transaction that is going to take more than
one assertion of FRAME_, the PCI Master continuously asserts its
request until the transaction has completed. For example, the PCI
Master continuously asserts requests during the first part of a two
part critical word first transaction.
If at least one command is pending within the PPC FIFO.
TBST* MEM C/BE
1101
0 1 1110
1111
Computer Group Literature Center Web Site
PCI Command
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate