Motorola MVME5100 Programmer's Reference Manual page 198

System Memory Controller (SMC)
Table 3-1. 60 x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100
3
4-Beat Write after 4-Beat Write,
SDRAM Bank Active - Page Hit
1-Beat Read after idle,
SDRAM Bank Inactive
1-Beat Read after idle,
SDRAM Bank Active - Page Miss
1-Beat Read after idle,
SDRAM Bank Active - Page Hit
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Miss
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Hit
1-Beat Write after idle,
SDRAM Bank Active or Inactive
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Miss
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Hit
3-8
SDRAMs (CAS_latency of 2) (Continued)
Access Type
Notes 1. SDRAM speed attributes are programmed for the
following: CAS_latency = 2, tRCD = 2 CLK Periods, tRP =
2CLK Periods, tRAS = 5 CLK Periods, tRC = 7 CLK
Periods, tDP = 2 CLK Periods, and the swr dpl bit is set in
the SDRAM Speed Attributes Register.
2. The Hawk is configured for "no external registers" on the
SDRAM control signals.
Access Time
3-1-1-1 3-1-1-1 for the second burst
write after idle.
2-1-1-1 for subsequent burst
writes.
10
12
7
8
5
5
13
8
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