Block Diagrams; Figure 3-1. Hawk Used With Synchronous Dram In A System - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)
3

Block Diagrams

Figure 3-1. Hawk Used with Synchronous DRAM in a System

3-2
ROM/Flash Interface
– Two blocks with each block being 16 or 64 bits wide.
– Programmable access time on a per-block basis.
2
I C master interface.
External status/control register support
Figure 3-1 depicts a Hawk as it would be connected with SDRAMs in a
system. Figure 3-2 shows the SMC's internal data paths.
the overall SDRAM connections.
SMC portion of the Hawk ASIC.
PowerPC
Data (64 Bits)
PowerPC
Data Parity (8 Bits)
PowerPC
Address &Control
PowerPC
Address Parity (4 bits)
Figure 3-4 shows a block diagram of the
SDRAM
Data (64 Bits)
HAWK SDRAM
Address & Control
SDRAM
Check Bits (8 Bits)
Computer Group Literature Center Web Site
Figure 3-3 shows
Synch
DRAM
Data
Check