I2C Sequential Read - Motorola MVME5100 Programmer's Reference Manual

2
I C Sequential Read
2
The I
(described here) or an I
The first step in the programming sequence of an I
initiation is to test the i2_cmplt bit for the operation-complete status. The
next step is to initiate a start sequence by first setting the i2_start and
i2_enbl bits in the I
(bits 7-1) and write bit (bit 0=0) to the I
i2_cmplt bit is automatically cleared with the write cycle to the I
Transmitter Data Register.
2
The I
i2_ackin bits. The i2_cmplt bit becomes set when the device address and
write bit are transmitted, and the i2_ackin bit provides status as to whether
or not a slave device acknowledged the device address. With the successful
transmission of the device address, the initial word address is loaded into
2
the I C Transmitter Data Register to be transmitted to the slave device.
Again, i2_cmplt and i2_ackin bits must be tested for proper response.
At this point, the slave device is still in a write mode. Therefore, another
start sequence must be sent to the slave to change the mode to read by first
setting the i2_start, i2_ackout, and i2_enbl bits in the I
and then writing the device address (bits 7-1) and read bit (bit 0=1) to the
2
I C Transmitter Data Register. After i2_cmplt and i2_ackin bits are tested
for proper response, the I
(data=don't care) to the I
master controller to initiate a read transmission from the slave device.
After the I
i2_datin=1 in the I
tested for proper status, the I
acknowledge and the system software may then read the data by polling
2
the I C Receiver Data Register.
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C sequential read can be initiated by either an I
2
C current address read.
2
C Control Register and then writing the device address
C Status Register must now be polled to test the i2_cmplt and
2
C master controller writes a dummy value
2
C Transmitter Data Register.This causes the I
2
C master controller has received a byte of data (indicated by
2
C Status Register) and the i2_cmplt bit has also been
2
2
C Transmitter Data Register. The
2
C master controller responds with an
Functional Description
2
C random read
C random read
2
C
2
C Control Register
2
C
3-31
3