Memory Maps; Processor Memory Map; Default Processor Memory Map; Table 1-2. Default Processor Memory Map - Motorola MVME5100 Programmer's Reference Manual

Product Data and Memory Maps
1

Memory maps

Processor Memory Map

Default Processor Memory Map

Processor Address
Start
0000 0000
8000 0000
8081 0000
FEF8 0000
1-4
The following sections describe the memory maps for the MVME5100.
The processor memory map configuration is under the control of the PCI
Host Bridge (PHB) and System Memory Controller (SMC) portions of the
Hawk ASIC. The Hawk adjusts system mapping to suit a given
application via programmable map decoder registers. At system power-up
or reset, a default processor memory map takes over.
Following a reset, the memory map presented to the processor is identical
to the CHRP memory map described in this document.
The MVME5100 is fully capable of supporting both the PREP and the
CHRP processor memory maps with ROM/FLASH size limited to 16MB
and RAM size limited to 2GB.
The default processor memory map that is valid at power-up or reset
remains in effect until reprogrammed for specific applications.
defines the entire default map ($00000000 to $FFFFFFFF).

Table 1-2. Default Processor Memory Map

End
7FFF FFFF 2GB
8080 FFFF 8M+64K
FEF7 FFFF 2GB-24MB-576KB
FEF8 FFFF 64KB
Size
Not Mapped
Zero-based PCI/ISA I/O Space
Not Mapped
System Memory Controller Registers
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Table 1-2
Definition