Motorola MVME5100 Programmer's Reference Manual page 312

Global Configuration Register
H
Hardware Control-Status Register
Hawk
address parity
as MPU/PCI bus bridge controller ASIC
1-15
block diagram
configuration options
data parity
ECC Codes
Error Correction Codes
error notification and handling
I2C Byte Write
I2C Current Address Read
I2C Page Write
I2C Random Read
I2C Sequential Read
MPIC control registers
MPIC interrupt assignments
MPIC interrupts
MPIC register map
PCI Host Bridge & Multi-Processor In-
terrupt Controller chip
programming details
programming ROM/Flash devices
SMC 3-1
software considerations
System Memory Controller block dia-
gram
used with DRAM in a system
writing to the control registers
Hawk ASIC 1-12
Hawk External Register Bus Summar
I
Hawk I2C interface and configuration infor-
N
mation
Hawk PCI Host Bridge
D
Hawk System Memory Controller
E
Hawk's DEVSEL_ pin
X
as criteria for PHB config. mapping
Hawk's I2C bus
IN-4
2-114
2-77
3-10
2-3
3-35
3-10
3-86
3-86
4-6
3-23
3-27
3-29
3-25
3-31
2-22
4-1
4-1
2-110
2-1
4-1
3-74
3-74
3-3
3-2
3-74
1-21
1-13
1-2
1-2
3-76
Hawk's PCI arbiter
priority schemes
Hawk's SMC
overview 3-1
HCSR
Hardware Control-Status Register
Header/Type Register
I
I/O Base Register
MPIC 2-102
I2C
Byte Write, Hawk
Current Address Read, Hawk
EEPROMs
Page Write, Hawk
Random Read, Hawk
Sequential Read, Hawk
I2C Receiver Data Register
IDSEL Mapping for PCI Devices
initializing
SDRAM-related control registers
Inter-Integrated Circuit
Internal Clock Frequency
Interprocessor Interrupt Dispatch Registers
2-126
Interrupt Acknowledge Registers
Interrupt Controller
features 2-2
Interrupt Enable control bits
interrupts
8259 4-3
Hawk MPIC
introduction 1-1
Hawk PHB/MPIC
PHB/MPIC
programming details for Hawk
SMC 3-1
IPI Vector/Priority Registers
L
2-19
L2 Cache 1-1, 1-9
Computer Group Literature Center Web Site
Index
2-35
2-77
2-101
3-23
3-27
3-76
3-29
3-25
3-31
3-66
1-19
3-75
1-13
1-1
2-127
1-2
3-47
4-1
2-1
2-1
4-1
2-117