External Interrupt Interface; Figure 2-8. Serial Mode Interrupt Scan - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2

External Interrupt Interface

2-52
If the OPIC bit (refer to the
section for more information) is enabled, the Hawk detected errors will be
passed on to MPIC. If the OPIC bit is disabled, Hawk detected errors are
passed directly to the processor 0 interrupt pin.
The external interrupt interface functions as either a parallel or a serial
interface depending on the EINTT bit in the MPIC Global Configuration
Register. If this bit is set, MPIC is in serial mode. Otherwise, MPIC
operates in the parallel mode.
In serial mode, all 16 external interrupts are serially scanned into MPIC
using the SI_STA and SI_DAT pins as shown in
In parallel mode, 16 external signal pins are used as interrupt inputs
(interrupts 0 through 15).
PCLK
SI_STA
SI_DAT
EXT0 EXT1 EXT2

Figure 2-8. Serial Mode Interrupt Scan

Using PCLK as a reference, external logic will pulse SI_STA one clock
period indicating the beginning of an interrupt scan period. On the same
clock period that SI_STA is asserted, external logic will feed the state of
EXT0 on the SI_DAT pin. External logic will continue to sequentially
place EXT1 through EXT15 on SI_DAT during the next 15 clock periods.
This process may be repeated at any rate, with the fastest possible next
assertion of SI_STA on the clock following the sampling of EXT15. Each
scan process must always scan exactly 16 external interrupts.
General Control-Status/Feature Registers
Figure
EXT13EXT14 EXT15
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2-8.