Interprocessor Interrupts (Ipi); 8259 Compatibility; Hawk Internal Errror Interrupt - Motorola MVME5100 Programmer's Reference Manual

Interprocessor Interrupts (IPI)

Processors 0 and 1 can generate interrupts which are targeted for the other
or both processors. There are four Interprocessor Interrupts (IPI) channels.
The interrupts are initiated by writing a bit in the IPI dispatch registers. If
subsequent IPI's are initiated before the first is acknowledged, only one IPI
will be generated. The IPI channels deliver interrupts in Direct Mode and
can be directed to more than one processor.

8259 Compatibility

The MPIC provides a mechanism to support PC-AT compatible chip sets
using the 8259 interrupt controller architecture. After power-on reset, the
MPIC defaults to 8259 pass-through mode. In this mode, if the OPIC is
enabled, interrupts from external source number 0 (the interrupt signal
from the 8259 is connected to this external interrupt source on the MPIC)
are passed directly to processor 0. If the pass-through mode is disabled and
the OPIC is enabled, the 8259 interrupts are delivered using the priority
and distribution mechanisms of the MPIC.
MPIC does not interact with the vector fetch from the 8259 interrupt
controller.

Hawk Internal Errror Interrupt

Hawk's PHB and SMC detected errors are grouped together and sent to the
interrupt logic as a singular interrupt source (Hawk internal error
interrupt). This Hawk internal error interrupt request is an active low-level
sensitive interrupt. The interrupt delivery mode for this interrupt is
distributed. When the OPIC is disabled, the Hawk internal error interrupt
will be passed directly on to processor 0 INT pin.
For system implementations where the MPIC controller is not used, the
Hawk internal error condition will be made available by a signal which is
external to the Hawk ASIC. Presumably this signal will be connected to an
externally sourced interrupt input of an MPIC controller of a different
device. Since the MPIC specification defines external I/O interrupts to
operate in the distributed mode, the delivery mode of this error interrupt
should be consistent.
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Multi-Processor Interrupt Controller (MPIC)
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