Motorola MVME5100 Programmer's Reference Manual page 123

Then one of these bits is delivered to each Interrupt Selector. Since this
interrupt source can be multicast, each of these IPR bits must be cleared
separately when the vector is returned for that interrupt to a particular
processor.
If one of the following sets of conditions is true, the interrupt pin for
processor 0 is driven active.
There is a possibility for a priority tie between the two processors when
resolving external interrupts. In that case, the interrupt will be delivered to
processor 0 or processor 1 as determined by the TIE mode bit. This case is
not defined in the above rule set.
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Set1
– The source ID in IRR_0 is from an external source.
– The destination bit for processor 1 is 0 for this interrupt.
– The priority from IRR_0 is greater than the highest priority in
ISR_0.
– The priority from IRR_0 is greater than the contents of task
register_0.
Set2
– The source ID in IRR_0 is from an external source.
– The destination bit for processor 1 is a 1 for this interrupt.
– The source ID in IRR_0 is not present is ISR_1.
– The priority from IRR_0 is greater than the highest priority in
ISR_0.
– The priority from IRR_0 is greater than the Task Register_0
contents.
– The contents of Task Register_0 is less than the contents of Task
Register_1.
Set3
– The source ID in IRR_0 is from an internal source.
– The priority from IRR_0 is greater than the highest priority in
ISR_0.
– The priority from IRR_0 is greater than the Task Register_0
contents.
Multi-Processor Interrupt Controller (MPIC)
2
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