Motorola MVME5100 Programmer's Reference Manual page 134

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
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2-72
XFBR PPC Flush Before Read. If set, the PHB will guarantee
that all PCI initiated posted write transactions will be
completed before any PPC-initiated read transactions will
be allowed to complete. When XFBR is clear, there is no
correlation between these transaction types and their order
of completion. Refer to the section titled
Ordering
XBTx PPC Bus Time-out. This field specifies the enabling and
PPC bus time-out length to be used by the PPC timer. The
time-out length is encoded as follows:
MBT
P64 64-bit PCI Mode. If set, the PHB is connected to a 64-bit
PCI bus. Refer to the section titled
Configuration
OPIC OpenPIC Interrupt Controller Enable. If set, the PHB
detected errors are passed on to the MPIC. If cleared, PHB
detected errors are passed on to the processor 0 INT pin.
XIDx PPC ID. This field is encoded as shown below to indicate
who is currently the PPC bus master. This information is
obtained by sampling the XARB0 thru XARB3 pins when
in external PPC arbitration mode. When in internal PPC
arbitration mode, this information is generated by the PPC
Arbiter. In a multiprocessor environment, these bits allow
software to determine on which processor it is currently
running.
MID
00
01
10
11
for more information.
Time Out Length
00 256 msec
01 64 msec
10 8 msec
11 disabled
for more details of how this bit is set.
Current PPC Data Bus
Master
device on ABG0*
device on ABG1*
device on ABG2
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