Motorola MVME5100 Programmer's Reference Manual page 317

rom_b_64 3-57
ROM_B_BASE 3-56
rom_b_en 3-57
rom_b_rv 3-57
rom_b_siz 3-57
rom_b_we 3-58
Row Address 3-52
rwcb 3-45
S
SBC mode 1-11
SBE_COUNT 3-50
scb0,scb1 3-51
scien 3-47
scof 3-50
scrub counter 3-51
Scrub Write Enable control bit
Scrub/Refresh Register
SMC 3-51
SDRAM
block organization 3-9
connections (block diagram)
Operational Method for Sizing
registers initializing
sizing 3-76
speed attributes 3-75
speeds 3-7
SDRAM Attributes Register
SMC 3-41
SDRAM Base Address Register
SMC 3-67
SDRAM Base Address/Enable
SDRAM Base Register
SMC 3-43
SDRAM Control Registers
Initialization Example
SDRAM Enable and Size Register
SMC 3-66
SDRAM Speed Attributes Register
SMC 3-68
Serial Presence Detect (SPD)
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3-51
3-4
3-83
3-75
3-76
3-77
3-76
Serial Presence Detect (SPD) Definitions
1-12
sien 3-48
Single Bit Error Counter
single-beat reads/writes
single-bit error 3-12
single-bit errors ordered by syndrome code
3-87
sizing SDRAM 3-76
SMC
32-Bit Counter 3-72
address parity 3-10
Address Parity Error Address Register
3-71
Address Parity Error Log Register
cache coherency 3-11
CLK Frequency Register
CSR Accesses 3-34
cycle types 3-11
data parity 3-10
Data Parity Error Upper Data Register
3-61
data transfers 3-9
ECC Control Register
Error Address Register
error correction 3-11
Error Logger Register
error logging 3-13
External Register Set
General Control Register
Hawk 1-4
L2 cache support 3-11
on Hawk 3-1
refresh/scrub 3-34
ROM A Base/Size Register
ROM B Base/Size Register
ROM Speed Attributes Register
Scrub/Refresh Register
SDRAM Base Address Register 3-43,
3-67
SDRAM Enable and Size Register 3-41,
3-66
3-50
3-6
3-70
3-44
3-45
3-51
3-49
3-34
3-39
3-53
3-56
3-58
3-51
IN-9
I
N
D
E
X