Motorola MVME5100 Programmer's Reference Manual page 136

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
2-74
PRI Priority. If set, the PPC Arbiter will impose a rotating
between CPU0 grants. If cleared, a fixed priority will be
established between CPU0 and CPU1 grants, with CPU0
having a higher priority than CPU1.
PRKx Parking. This field determines how the PPC Arbiter will
implement CPU parking. The encoding of this field is
shown in the table below.
PRK
00
01
10
11
ENA Enable. This read only bit indicates the enabled state of
the PPC Arbiter. If set, the PPC Arbiter is enabled and is
acting as the system arbiter. If cleared, the PPC Arbiter is
disabled and external logic is implementing the system
arbiter. Refer to the section titled
Configuration
set.
The PCI Arbiter Register (PARB) provides control and status for the PCI
Arbiter. Refer to the section titled
bits within the PARB register are defined as follows:
PRIx Priority. This field is used by the PCI Arbiter to establish
a particular bus priority scheme. The encoding of this field
is shown in the following table.
PRI
00
01
10
11
CPU Parking
None
Park on last CPU
Park always on CPU0
Park always on CPU1
for more information on how this bit gets
PCI Arbiter for more informatiion. The
Priority Scheme
Fixed
Round Robin
Mixed
Reserved
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