Wdtxcntl Registers - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2

WDTxCNTL Registers

Address
Bit
Name
Operation
Reset
2-92
The PPC Slave Attributes Register 3 (XSATT3) contains attribute
information associated with the mapping of PPC memory space to PCI I/O
space. The bits within the XSATT3 register are defined as follows:
REN Read Enable. If set, the corresponding PPC Slave is
enabled for read transactions.
WEN Write Enable. If set, the corresponding PPC Slave is
enabled for write transactions.
WPEN Write Post Enable. If set, write posting is enabled for the
corresponding PPC Slave.
IOM PCI I/O Mode. If set, the corresponding PPC Slave
generates PCI I/O cycles using spread addressing as
defined in the section on
clear, the corresponding PPC Slave generates PCI I/O
cycles using contiguous addressing.
WDT1CNTL - $FEFF0060
WDT2CNTL - $FEFF0068
KEY
W R
$00 00
The Watchdog Timer Control Registers (WDT1CNTL and
WDT2CNTL) are used to provide control information to the watchdog
timer functions within the PHB. The fields within WDTxCNTL registers
are defined as follows:
Generating PCI
WDTxCNTL
RES
R/W
$7 or $8
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Cycles. When
RELOAD
R/W
$FF