Motorola MVME5100 Programmer's Reference Manual page 75

Table 2-4. PPC Master Read Ahead Options (Continued)
RXFT RMFT
00 xx
xx 00
01 xx
xx 01
10 xx
xx 10
11 xx
xx 11
Upon completion of a prefetched read transaction, any residual read data
left within the PCI FIFO will be invalidated (discarded). The PHB does not
have a mechanism for snooping the PPC60x bus for transactions associated
with the prefetched read data within the PCI FIFO. Therefore, caution
should be exercised when using the prefetch option within coherent
memory space.
The PPC Master never performs prefetch reads beyond the address range
mapped within the PCI Slave map decoders. As an example, assume PHB
has been programmed to respond to PCI address range $10000000 through
$1001FFFF with an offset of $2000. The PPC Master performs its last read
on the PPC60x bus at cache line address $3001FFFC or word address
$3001FFF8.
http://www.motorola.com/computer/literature
PCI
RAEN
Command
1 Read
Read Line
x Read Mul-
tiple
1 Read
Read Line
x Read Mul-
tiple
1 Read
Read Line
x Read Mul-
tiple
1 Read
Read Line
x Read Mul-
tiple
Initial
Continuation
Read Size
4 cache FIFO <= 0
lines cache lines
4 cache FIFO <= 1
lines cache line
4 cache FIFO <= 2
lines cache lines
4 cache FIFO <= 3
lines cache lines
Functional Description
Subsequent
Read Size
FIFO >= 4
cache lines
FIFO >= 4
cache lines
FIFO >= 4
cache lines
FIFO >= 4
cache lines
2-13
2