Motorola MVME5100 Programmer's Reference Manual page 17

List of Tables
Table 1-1. MVME Key Features ................................................................................1-1
Table 1-2. Default Processor Memory Map...............................................................1-4
Table 1-3. Suggested CHRP Memory Map ...............................................................1-6
Table 1-4. Hawk PPC Register Values for Suggested Memory Map.........................1-7
Table 1-5. I2C Device Addressing ...........................................................................1-14
Table 1-6. PCI Arbitration Assignments..................................................................1-15
Table 1-7. IDSEL Mapping for PCI Devices...........................................................1-19
Table 1-8. On-Board PCI Device Identification ......................................................1-20
Table 1-9. Hawk External Register Bus Summary ..................................................1-21
Table 1-10. 16550 Access Registers ........................................................................1-23
Table 1-11. MVME5100 Status Register .................................................................1-24
Table 1-12. MODFAIL Bit Register ........................................................................1-25
Table 1-13. MODRST Bit Register..........................................................................1-26
Table 1-14. TBEN Bit Register ................................................................................1-27
Table 1-15. M48T37V Access Registers .................................................................1-28
Table 1-16. Extended Features Register 1................................................................1-31
Table 1-17. Extended Features Register 2................................................................1-33
Table 2-1. PPC Slave Response Command Types .....................................................2-8
Table 2-2. PPC Master Transaction Profiles and Starting Offsets ...........................2-11
Table 2-3. PPC Master Write Posting Options.........................................................2-12
Table 2-4. PPC Master Read Ahead Options...........................................................2-12
Table 2-5. PPC Master Transfer Types ....................................................................2-14
Table 2-6. PPC Arbiter Pin Assignments.................................................................2-15
Table 2-7. PCI Slave Response Command Types....................................................2-23
Table 2-8. PCI Master Command Codes .................................................................2-27
Table 2-9. PCI Arbiter Pin Description....................................................................2-34
Table 2-10. Fixed Mode Priority Level Setting .......................................................2-35
Table 2-11. Mixed Mode Priority Level Setting ......................................................2-36
Table 2-12. Arbitration Setting ................................................................................2-37
Table 2-13. Address Modification for Little Endian Transfers................................2-40
Table 2-14. WDTxCNTL Programming ..................................................................2-44
Table 2-15. PHB Hardware Configuration ..............................................................2-50
Table 2-16. PPC Register Map for PHB ..................................................................2-68
Table 2-17. PCI Configuration Register ..................................................................2-97
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