Motorola DSP96002 User Manual page 839

32-bit digital signal processor
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MPYS//SUB
Operation:
S1.L * S2.L
D1.M:D1.L
(parallel data bus move)
D2.L - S3.L
D2.L
Description:
Multiply the two signed operands S1 and S2 and store the product in the specified destination register D1.
The two source operands S1and S2 are 32-bit integers and are taken from the low portion of S1 and S2.
The result is a 64-bit signed integer stored in the middle and low portions of D1.
Simultaneously, subtract the low portion of the specified source operand S3 from the low portion of the des-
tination operand D2 and store the result in the low portion of the destination operand D2.
This instruction is enabled only in Integer Mode.
Input Operand(s) Precision: 32-bit integer.
Subtraction Output Operand Precision: 32-bit integer.
Multiplication Output Operand Precision: 64-bit integer.
CCR Condition Codes:
C
V
Z
N
I
LR
R
A
ER Status Bits:
IER Flags:
MOTOROLA
Integer Signed
Multiply and Subtract
- Set if borrow is generated from the MSB of the subtraction result. Cleared
otherwise.
- Set if the subtraction result overflows. Cleared otherwise.
- Set if result of the subtraction is zero. Cleared otherwise.
- Set if result of the subtraction is negative. Cleared otherwise.
- Not affected.
- Not affected.
- Not affected.
- Not affected.
Not affected
Not affected
Assembler Syntax:
MPYS S1,S2,D1 SUB S3,D2
(move syntax - see the MOVE instruction de-
scription.)
MPYS S2,S1,D1 SUB S3,D2
(move syntax - see the MOVE instruction de-
scription.)
MPYS//SUB
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