Motorola DSP96002 User Manual page 5

Figure 2-1. DSP96002 Functional Group Pin Allocation
— — — –
MODB/ I R Q B(Mode Select B/External Interrupt Request B) - active low input, internally synchronized
to the input clock (CLK). MODB/
ing hardware reset and becomes a level sensitive or negative edge triggered, maskable
interrupt request input during normal instruction processing. MODA, MODB and MODC
select one of 8 initial chip operating modes, latched into the operating mode register
(OMR) when the
chronous to the input clock (CLK), multiple processors can be resynchronized using the
WAIT instruction and asserting
— — — –
MODC/ I R Q C(Mode Select C/External Interrupt Request C) - active low input, internally synchronized
to the input clock (CLK). MODC/
2 - 2
CPU Pins
Reset and IRQs
Clock Input
OnCE Port
CPU Spare
Quiet Power
Quiet Ground
CPU Subtotal
Power/Ground Planes
Package Noisy Power Plane
Package Noisy Ground Plane
Package Quiet Power Plane
Package Quiet Ground Plane
Power/Ground Plane Subtotal
Each Port Both Ports
Port A/B Pins
Data Bus 32
Address Bus 32
Data Power 2
Data Ground 4
Address Power 2
Address Ground 4
Addr/Data Subtotal 76
Each Port Both Ports
Port A/B Pins
Bus Control Signals 17
Bus Control Spare 2
Bus Control Power 1
Bus Control Ground 2
Control Subtotal 22
Pinout Summary
CPU Pins
Package Power/Ground Planes
Port A/B Pins
Data and Address
Bus Control
TOTALS
—
— — — —
R E S E
—
—
DSP96002 USER'S MANUAL
Pins
4
1
4
1
4
4
18
Pins
2
5
1
1
9
Pins
64
64
4
8
4
8
152
Pins
34
4
2
4
44
Pins
18
9
152
44
223
— — –
I R Q B selects the initial chip operating mode dur-
–
T pin is deasserted. If
— — –
I R Q B to exit the wait state.
— — –
I R Q C selects the initial chip operating mode dur-
— — — –
I R Q B is asserted syn-
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