Motorola DSP96002 User Manual page 801

3.1 CHANGE TO THE PROGRAMMING MODEL (INTEGER MODE)
To support the integer mode, bit 25 of the status register now features a new integer mode
(IM) bit as shown in Figure 3.
When the IM bit is cleared (0) the integer mode is disabled. When the IM bit is set, the
processor is in integer mode. The IM bit is cleared during reset.
31 30 29
LF
*
23 22
R1 R0
*
15 14
UN
CC NAN NAN
7 6
A R LR
3.1.1 Switching Into Integer Mode
The correct sequence for switching from the floating-point mode to integer mode is:
ORI #2,mr
NOP
NOP
parallel integer operation
4 SINGLE PRECISION MODE
The efficiency of the data ALU register file has been improved with the definition of the
new single precision mode (SPM), where the user has access to two data ALU register
files: a 10 floating-point register file (d0.h..d9.h, d0.m..d9.m) and a 10 integer register file
(d0.l..d9.l). If the program uses only single-precision MOVE operations and floating-point
MOTOROLA
28 27
I1 I0 FZ
21 20 19
SIOP SOVF SUNF SDZ
13 12 11
S OP
ERR OVF
5 4 3
I N
Figure 3 - DSP96002 Programming Model
; set the IM bit in MR register
; pipeline delay
; pipeline delay
26 25 24
MP IM
*
18 17 16
SINX
10 9 8
UNF DZ INX
2 1 0
Z V C
MR
Integer Mode
Flush to Zero
Interrupt Mask
IER
ER
CCR
Reserved
Multiply
Reserved
Loop Flag
19