Motorola DSP96002 User Manual page 149

which are maskable. Additionally, each of these interrupts has independent enable control. When the IRQA,
IRQB or IRQC interrupts are disabled in the interrupt priority register, pending requests will be discarded,
no new requests will be accepted, and the edge-detection latch will remain in the reset state. Also, if the
interrupt is defined as level-sensitive, its edge-detection latch will remain in the reset state.
Interrupt service, which begins by fetching the instruction word in
finished when the instruction word in the second vector location is fetched. In the
tive interrupt, the internal latch is automatically cleared when the second vector location is fetched. The fetch
of the first vector location does not guarantee that the second location will be fetched. Figure 8.7 illustrates
the one case where the second vector location is not fetched. In Figure 8.7, the (F)TRAPcc instruction "dis-
cards" the fetch of the first interrupt vector to ensure that the (F)TRAPcc vectors will be fetched. Instruction
n4 is decoded as a (F)TRAPcc while ii1 is being fetched. Execution of the (F)TRAPcc requires that ii1 be
discarded and the two (F)TRAPcc vectors (ii3 and ii4) be fetched instead.
8.4.4 (F)TRAPcc (Conditional Software Interrupt Instruction)
The (F)TRAPcc instruction causes a non-maskable interrupt which is serviced immediately following the
(F)TRAPcc instruction if the specified condition is true. (F)TRAPcc is a priority 3 interrupt.
Int ctl cyc1
Int ctl cyc2
Fetch
Decode
Execute
i = interrupt request
i* = interrupt request generated by (F)TRAPcc
ii1 = first vector of interrupt i
ii3 = first (F)TRAPcc vector (one word JSR)
ii4 = second (F)TRAPcc vector
n = normal instruction word
n4 = (F)TRAPcc, cc condition true
tr = instructions pertaining to the (F)TRAPcc long interrupt routine
Figure 8-7. (F)TRAPcc Instruction Rejecting Another Interrupt
On all level-sensitive interrupts, the Interrupt must be externally released before
interrupts are internally re-enabled or the processor will be interrupted repeatedly
until the interrupt is released.
MOTOROLA
i
i
n3 n4 ii1
n2 n3 trap --
n1 n2 n3 trap
DSP96002 USER'S MANUAL
the first vector location, is considered
i *
i
ii3 ii4
-- -- -- JSR
-- -- -- --
CAUTION
case of an edge-sensi-
tr1 tr2 tr3
-- tr1 tr2
JSR -- tr1
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