Motorola DSP96002 User Manual page 439

32-bit digital signal processor
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Move
IFcc.U
Operation:
If cc, then opcode operation
S
D
Description:
If the specified integer condition is true, transfer data from the specified source S to the specified destina-
tion D. Also, store result(s) of the specified Data ALU operation and update the CCR, ER and IER regis-
ters with the status information generated by the Data ALU operation. If the specified condition is false,
no destinations are altered and the status register is not affected. The UNCC bit in the ER register is never
updated by the Data ALU operation. If no register move is specified, this instruction is assembled with a
R0 to R0 move.
"cc" may specify the following conditions:
Mnemonic
CC (HS) - carry clear (higher or same)
CS (LO) - carry set (lower)
EQ
GE
GT
HI
LE
LS
LT
MI
NE(Q)
PL
VC
VS
AL
See restrictions in Section A.10.6 concerning Rn, Mn, and Nn registers as a
destination.
MOTOROLA
Integer iF
Conditional Instruction
with CCR, ER, and IER Update
- equal
- greater or equal
- greater than
- higher
- less or equal
- lower or same
- less than
- minus
- not equal
- plus
- overflow clear
- overflow set
- always true
DSP96002 USER'S MANUAL
Assembler Syntax:
Opcode-Operands
Condition
C = 0
C = 1
Z = 1
N && V = 0
Z v (N && V) = 0
Z v C = 0
Z v (N && V) = 1
Z v C = 1
N && V = 1
N = 1
Z = 0
N = 0
V = 0
V = 1
n.a.
CAUTION
Move
IFcc.U
S,D
IFcc.U
IFcc.U
A - 251

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