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7
**
31
....
**
**
7
HDMA
31
....
**
**
31
32-bit receive data register
31
32-bit transmit data register
HOST INTERFACE DSP96002 ADDRESS MAP
ADDR
X:$FFFFFFEC
X:$FFFFFFED
X:$FFFFFFEE
X:$FFFFFFEF
X:$FFFFFFE4
X:$FFFFFFE5
X:$FFFFFFE6
X:$FFFFFFE7
**
- reserved, read as zero, should be written with zero
for future compatibility.
7.4.6 Host Transmit Data Register and HMRC Clear (HTXC) - DSP96002 Side
The Host Transmit register and HMRC Clear (HTXC) is used for DSP96002 to host processor data trans-
fers in conjunction with "TX register write (address) and X/Y/P Memory Read (data) Interrupt" host func-
tions. The HTXC register is viewed as a 32-bit write-only register by the DSP96002. Writing the HTXC
register clears HTDE, HPRP, HXRP and HYRP. The HTXC register is transferred as 32-bit data to the
Receive Register RX if both the HTDE bit and the Receive Data Full RXDF status bit are cleared. This
transfer operation sets RXDF and HTDE, and clears HMRC (See Section 7.4.21.10).
7 - 16
6
5
4
**
HRES
HF3
HF2 HCIE HTIE HRIE
14
13
12
11
**
HYWE HYRE HXWE HXRE HPWE HPRE
6
5
4
**
**
HF1
HF0
14
13
12
11
**
HYWP HYRP HXWP HXRP HPWP HPRP
(HEX)
DSP96002
READ
HCRA
HSRA
----
HRXA
HCRB
HSRB
----
HRXB
Figure 7-10. HI - DSP96002 Programming Model
DSP96002 USER'S MANUAL
3
2
1
0
10
9
8
3
2
1
0
HCP HTDE HRDF
10
9
8
0
0
DSP96002
WRITE
HCRA
----
HTXCA
HTXA
HCRB
----
HTXCB
HTXB
READ/WRITE
HOST CONTROL
REGISTER
HCR
READ-ONLY
HOST STATUS
REGISTER
HSR
READ-ONLY
HOST RECEIVE
DATA REGISTER
HRX
WRITE-ONLY
HOST TRANSMIT
DATA REGISTER
HTX or HTXC
PORT A
PORT B
MOTOROLA
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