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31
31
30
29
DE
DIE
*
23
22
21
DCP
*
*
15
14
13
*
M6
M5
7
6
5
*
*
DSS2 DSS1 DSS0 DDS2 DDS1 DDS0
Figure 7-26. DMA Controller Programming Model - Channel 1
7.5.3 DMA Control/Status Register (DCS)
The DMA Control/Status Register (DCS) is a 32-bit read/write register that controls the DMA operation.
Each bit is described in the following paragraphs.
7 - 46
DMA Source Modifier Register
0
DSM1
addr X:$FFFFFFD7
DMA Source Address Register
DSR1
addr X:$FFFFFFD6
DMA Source Offset Register
DSN1
addr X:$FFFFFFD5
DMA Destination Modifier Register
DDM1
addr X:$FFFFFFD3
DMA Destination Address Register
DDR1
addr X:$FFFFFFD2
DMA Destination Offset Register
DDN1
addr X:$FFFFFFD1
DMA Counter
DCO1
addr X:$FFFFFFD4
28
27
26
25
DTD
*
DTM1 DTM0 DMAP
20
19
18
17
*
*
*
*
12
11
10
9
M4
M3
M2
M1
4
3
2
1
DSP96002 USER'S MANUAL
24
DMA Control/Status Register
addr X:$FFFFFFD0
16
*
8
M0
0
DCS1
MOTOROLA
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