Motorola DSP96002 User Manual page 328

32-bit digital signal processor
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FMPY//FADD.X
Operation:
S1 * S2
ROUND(SEP)
(parallel data bus move)
S3 + D2
ROUND(SEP)
Description:
Multiply the two operands S1 and S2, round to single extended precision and store the result in the spec-
ified destination register D1. Simultaneously, add the two operands S3 and D2, round to single extended
precision and store the result in the destination operand D2.
Input Operand(s) Precision: SEP Floating-Point.
Addition Output Operand Precision: SEP Floating-Point.
Multiplication Output Operand Precision: SEP Floating-Point.
CCR Condition Codes:
C
V
Z
N
I
LR
R
A
ER Status Bits:
INX
DZ
UNF
OVF
OPERR-Set if one of the multiply operands is infinity and the other is zero. Set if the addition
SNAN -Set if anyone of the source operands is a signaling NaN. Cleared otherwise.
NAN
UNCC -Always cleared.
A - 140
Floating-Point
Multiply and Add
D1
D2
- Not affected.
- Not affected.
- Set if result of the addition is zero. Cleared otherwise.
- Set if result of the addition is negative. Cleared otherwise.
- Set if result of the addition is infinity. Cleared otherwise.
- Not affected.
- Not affected.
- Not affected.
-Set if the result of the addition or the multiplication is inexact. Cleared otherwise.
-Always cleared.
-Set if the result of the addition or the multiplication underflows. Cleared otherwise.
-Set if the result of the addition or the multiplication overflows. Cleared otherwise.
operands are opposite-signed infinities. Cleared otherwise.
-Set if result of the addition is a NaN. Cleared otherwise.
DSP96002 USER'S MANUAL
FMPY//FADD.X
Assembler Syntax:
FMPY S1,S2,D1 FADD.X S3,D2
(move syntax - see the MOVE instruction descrip-
tion.)
FMPY S2,S1,D1 FADD.X S3,D2
(move syntax - see the MOVE instruction descrip-
tion.)
MOTOROLA

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