Motorola DSP96002 User Manual page 150

I 1 I0
0 0
0 1
1 0
1 1
Figure 8-8. Status Register Interrupt Mask Bits
31 30 29
** ** **
23 22 21
HBL1 HBL0 HAL1 HAL0 D1L1 D1L0 D0L1 D0L0
15 14 13
** ** **
7 6 5
IRBS IBL2 IBL1 IBL0 IRAS IAL2 IAL1 IAL0
Note: Reserved bits read as zero and should be written with zero
for future compatibility.
Figure 8-9. Interrupt Priority Register IPR (Address X:$FFFFFFFF)
8 - 10
Exceptions Permitted
IPL 0, 1, 2, 3
IPL 1, 2, 3
IPL 2, 3
IPL 3
28 27 26 25
** ** ** **
20 19 18 17
12 11 10 9
** IRCS ICL2 ICL1 ICL0
4 3 2 1
DSP96002 USER'S MANUAL
Exceptions
Masked
None
IPL 0
IPL 0,1
IPL 0,1,2
24
**
Reserved
16
DMA Channel 0 IPL
DMA Channel 1 IPL
Host A IPL
Host B IPL
8
IRQC IPL
IRQC Trigger Mode
IRQC Status
Reserved
0
IRQA IPL
IRQA Trigger Mode
IRQA Status
IRQB IPL
IRQB Trigger Mode
IRQB Status
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